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參數(shù)資料
| 型號(hào)： | GS8662D18GE-333I |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | 72Mb SigmaQuad-II Burst of 4 SRAM |
| 中文描述： | 4M X 18 DDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165 |
| 文件頁(yè)數(shù)： | 8/29頁(yè) |
| 文件大小： | 896K |
| 代理商： | GS8662D18GE-333I |
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Preliminary
GS8662D08/09/18/36E-333/300/250/200/167
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.01a 2/2006
8/29
2005, GSI Technology
SigmaQuad-II B4 SRAM DDR Write
The status of the Address Input, W, and R pins are sampled by the rising edges of K. W and R high causes chip disable. A low on
the Write Enable-bar pin, W, and a high on the Read Enable-bar pin, R, begins a write cycle. W is always ignored if the previous
command was a write command. Data is clocked in by the next rising edge of K, the rising edge of K after that, the next rising edge
of K, and finally by the next rising edge of K. and by the rising edge of the K that follows.
SigmaQuad-II B4 Double Data Rate SRAM Write First
Write A
NOP
Read B
Write C
Read D
Write E
NOP
A
B
C
D
E
A
A+1
A+2
A+3
C
C+1
C+2
C+3
E
E+1
E+
A
A+1
A+2
A+3
C
C+1
C+2
C+3
E
E+1
E+
B
B+1
B+2
B+3
D
D+1
D+2
K
K
Address
R
W
BWx
D
C
C
Q
CQ
CQ
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS8662D36E-167 | 72Mb SigmaQuad-II Burst of 4 SRAM |
| GS8662D36E-167I | 72Mb SigmaQuad-II Burst of 4 SRAM |
| GS8662D36E-200 | 72Mb SigmaQuad-II Burst of 4 SRAM |
| GS8662D36E-200I | 72Mb SigmaQuad-II Burst of 4 SRAM |
| GS8662D36E-250 | 72Mb SigmaQuad-II Burst of 4 SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS8662D19BD-300 | 制造商:GSI Technology 功能描述:165 FBGA - Bulk |
| GS8662D19BD-400 | 制造商:GSI Technology 功能描述:165 FBGA - Bulk |
| GS8662D19BD-450 | 制造商:GSI Technology 功能描述:165 FBGA - Bulk |
| GS8662D20BD-450 | 制造商:GSI Technology 功能描述:165 FBGA - Bulk |
| GS8662D20BD-500 | 制造商:GSI Technology 功能描述:165 FBGA - Bulk |
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