欧美成人免费电影,国产欧美一区二区三区精品酒店,精品国产a毛片,色网在线免费观看

參數資料
型號: GS8662D36E-200I
廠商: GSI TECHNOLOGY
元件分類: DRAM
英文描述: 72Mb SigmaQuad-II Burst of 4 SRAM
中文描述: 2M X 36 DDR SRAM, 0.45 ns, PBGA165
封裝: 15 X 17 MM, 1 MM PITCH, FPBGA-165
文件頁數: 13/29頁
文件大小: 896K
代理商: GS8662D36E-200I
Preliminary
GS8662D08/09/18/36E-333/300/250/200/167
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.01a 2/2006
13/29
2005, GSI Technology
FLXDrive-II Output Driver Impedance Control
HSTL I/O SigmaQuad-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to
V
SS
via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be
5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is
between 150
and 300
. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts
in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and
temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance
evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is
implemented with discrete binary weighted impedance steps. Updates of pull-down drive impedance occur whenever a driver is
producing a “1” or is High-Z. Pull-up drive impedance is updated when a driver is producing a “0” or is High-Z.
Separate I/O SigmaQuad-II B4 SRAM Truth Table
Previous
Operation
A
R
W
Current
Operation
D
D
D
D
Q
Q
Q
Q
K
(t
n-1
)
K
(t
n
)
K
(t
n
)
K
(t
n
)
K
(t
n
)
K
(t
n+1
)
K
(t
n+1
)
K
(t
n+2
)
K
(t
n+2
)
K
(t
n+1
)
K
(t
n+1
)
K
(t
n+2
)
K
(t
n+2
)
Deselect
X
1
1
Deselect
X
X
Hi-Z
Hi-Z
Write
X
1
X
Deselect
D2
D3
Hi-Z
Hi-Z
Read
X
X
1
Deselect
X
X
Q2
Q3
Deselect
V
1
0
Write
D0
D1
D2
D3
Hi-Z
Hi-Z
Deselect
V
0
X
Read
X
X
Q0
Q1
Q2
Q3
Read
V
X
0
Write
D0
D1
D2
D3
Q2
Q3
Write
V
0
X
Read
D2
D3
Q0
Q1
Q2
Q3
Notes:
1.
2.
3.
4.
5.
“1” = input “high”; “0” = input “low”; “V” = input “valid”; “X” = input “don’t care”
“—” indicates that the input requirement or output state is determined by the next operation.
Q0, Q1, Q2, and Q3 indicate the first, second, third, and fourth pieces of output data transferred during Read operations.
D0, D1, D2, and D3 indicate the first, second, third, and fourth pieces of input data transferred during Write operations.
Qs are tristated for one cycle in response to Deselect and Write commands, one cycle after the command is sampled, except when pre-
ceded by a Read command.
Users should not clock in metastable addresses.
6.
相關PDF資料
PDF描述
GS8662D36E-250 72Mb SigmaQuad-II Burst of 4 SRAM
GS8662D36E-250I 72Mb SigmaQuad-II Burst of 4 SRAM
GS8662D36E-300 72Mb SigmaQuad-II Burst of 4 SRAM
GS8662D36E-300I 72Mb SigmaQuad-II Burst of 4 SRAM
GS8662D36E-333 72Mb SigmaQuad-II Burst of 4 SRAM
相關代理商/技術參數
參數描述
GS8662D36E-250 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb SigmaQuad-II Burst of 4 SRAM
GS8662D36E-250I 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb SigmaQuad-II Burst of 4 SRAM
GS8662D36E-300 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb SigmaQuad-II Burst of 4 SRAM
GS8662D36E-300E 制造商:GSI Technology 功能描述:165 FBGA - Bulk
GS8662D36E-300I 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb SigmaQuad-II Burst of 4 SRAM
主站蜘蛛池模板: 西青区| 巢湖市| 沁水县| 北海市| 济宁市| 双峰县| 白河县| 百色市| 文成县| 威宁| 丹巴县| 上犹县| 高尔夫| 开远市| 肃宁县| 光山县| 永昌县| 酉阳| 静安区| 德安县| 六枝特区| 黎川县| 郧西县| 安阳县| 九台市| 司法| 平南县| 樟树市| 汉源县| 澄江县| 东丽区| 孟连| 湟源县| 奇台县| 黔东| 昌乐县| 梨树县| 丰镇市| 盐池县| 西林县| 株洲县|