欧美成人免费电影,国产欧美一区二区三区精品酒店,精品国产a毛片,色网在线免费观看

參數資料
型號: GS8662D36E-250I
廠商: GSI TECHNOLOGY
元件分類: DRAM
英文描述: 72Mb SigmaQuad-II Burst of 4 SRAM
中文描述: 2M X 36 DDR SRAM, 0.45 ns, PBGA165
封裝: 15 X 17 MM, 1 MM PITCH, FPBGA-165
文件頁數: 7/29頁
文件大小: 896K
代理商: GS8662D36E-250I
Preliminary
GS8662D08/09/18/36E-333/300/250/200/167
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.01a 2/2006
7/29
2005, GSI Technology
Background
Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are
needed. Therefore, the SigmaQuad-II SRAM interface and truth table are optimized for alternating reads and writes. Separate I/O
SRAMs are unpopular in applications where multiple reads or multiple writes are needed because burst read or write transfers from
Separate I/O SRAMs can cut the RAM’s bandwidth in half.
Alternating Read-Write Operations
SigmaQuad-II SRAMs follow a few simple rules of operation.
- Read or Write commands issued on one port are never allowed to interrupt an operation in progress on the other port.
- Read or Write data transfers in progress may not be interrupted and re-started.
- R and W high always deselects the RAM.
- All address, data, and control inputs are sampled on clock edges.
In order to enforce these rules, each RAM combines present state information with command inputs. See the Truth Table for
details.
SigmaQuad-II B4 SRAM DDR Read
The status of the Address Input, W, and R pins are sampled by the rising edges of K. W and R high causes chip disable. A low on
the Read Enable-bar pin, R, begins a read cycle. R is always ignored if the previous command loaded was a read command. Data
can be clocked out after the next rising edge of K with a rising edge of C (or by K if C and C are tied high), after the following
rising edge of K with a rising edge of C (or by K if C and C are tied high), after the next rising edge of K with a rising edge of C,
and after the following rising edge of K with a rising edge of C. Clocking in a high on the Read Enable-bar pin, R, begins a read
port deselect cycle.
SigmaQuad-II B4 Double Data Rate SRAM Read First
Read A
NOP
Read B
Write C
Read D
Write E
NOP
A
B
C
D
E
C
C+1
C+2
C+3
E
E+1
C
C+1
C+2
C+3
E
E+1
A
A+1
A+2
A+3
B
B+1
B+2
B+3
D
D+1
D+2
K
K
Address
R
W
BWx
D
C
C
Q
CQ
CQ
相關PDF資料
PDF描述
GS8662D36E-300 72Mb SigmaQuad-II Burst of 4 SRAM
GS8662D36E-300I 72Mb SigmaQuad-II Burst of 4 SRAM
GS8662D36E-333 72Mb SigmaQuad-II Burst of 4 SRAM
GS8662D36E-333I 72Mb SigmaQuad-II Burst of 4 SRAM
GS8662D36GE-167 72Mb SigmaQuad-II Burst of 4 SRAM
相關代理商/技術參數
參數描述
GS8662D36E-300 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb SigmaQuad-II Burst of 4 SRAM
GS8662D36E-300E 制造商:GSI Technology 功能描述:165 FBGA - Bulk
GS8662D36E-300I 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb SigmaQuad-II Burst of 4 SRAM
GS8662D36E-333 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb SigmaQuad-II Burst of 4 SRAM
GS8662D36E-333I 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb SigmaQuad-II Burst of 4 SRAM
主站蜘蛛池模板: 彩票| 玉龙| 巨野县| 青冈县| 砚山县| 左云县| 额敏县| 阿勒泰市| 普格县| 腾冲县| 温州市| 榆树市| 大关县| 葫芦岛市| 班戈县| 杭锦旗| 旺苍县| 阜宁县| 柞水县| 长治县| 寿宁县| 治县。| 汶上县| 南溪县| 平顺县| 寿阳县| 增城市| 修文县| 专栏| 沁源县| 葵青区| 张家口市| 龙南县| 高邮市| 平安县| 陇南市| 商水县| 黄浦区| 晋宁县| 泰安市| 永寿县|