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參數(shù)資料
型號(hào)： GS8662Q09GE-167
廠商： GSI TECHNOLOGY
元件分類(lèi)： DRAM
英文描述： 72Mb SigmaQuad-II Burst of 2 SRAM
中文描述： 8M X 9 STANDARD SRAM, 0.5 ns, PBGA165
封裝： 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165
文件頁(yè)數(shù)： 26/35頁(yè)
文件大小： 993K
代理商： GS8662Q09GE-167
Preliminary
GS8662Q08/09/18/36E-300/250/200/167
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.01 9/2005
26/35
2005, GSI Technology
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
Instruction Register
ID Code Register
·
31 30 29
Boundary Scan Register
0
1
2
0
· · ·
1
2
0
Bypass Register
TDI
TDO
TMS
TCK
Test Access Port (TAP) Controller
1
·
1
0
·
·
·
·
·
·
·
·
·
Control Signals
·
JTAG TAP Block Diagram
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
相關(guān)PDF資料
PDF描述
GS8662Q09GE-167I 72Mb SigmaQuad-II Burst of 2 SRAM
GS8662Q09GE-200 72Mb SigmaQuad-II Burst of 2 SRAM
GS8662Q09GE-200I 72Mb SigmaQuad-II Burst of 2 SRAM
GS8662Q09GE-250 72Mb SigmaQuad-II Burst of 2 SRAM
GS8662Q09GE-250I 72Mb SigmaQuad-II Burst of 2 SRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS8662Q09GE-167I 制造商:GSI 制造商全稱(chēng):GSI Technology 功能描述:72Mb SigmaQuad-II Burst of 2 SRAM
GS8662Q09GE-200 制造商:GSI 制造商全稱(chēng):GSI Technology 功能描述:72Mb SigmaQuad-II Burst of 2 SRAM
GS8662Q09GE-200I 制造商:GSI 制造商全稱(chēng):GSI Technology 功能描述:72Mb SigmaQuad-II Burst of 2 SRAM
GS8662Q09GE250 制造商:GSI TECHNOLOGY 功能描述:
GS8662Q09GE-250 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 72MBIT 8MX9 0.45NS 165FBGA - Trays
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