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參數資料
| 型號： | GS8662R18E-300 |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | 72Mb SigmaCIO DDR-II Burst of 4 SRAM |
| 中文描述： | 4M X 18 DDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 15 MM X 17 MM, 1MM PITCH, FPBGA-165 |
| 文件頁數： | 1/37頁 |
| 文件大小： | 942K |
| 代理商： | GS8662R18E-300 |
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Preliminary
GS8662R08/09/18/36E-333/300/250/200/167
72Mb SigmaCIO DDR-II
Burst of 4 SRAM
333 MHz–167 MHz
1.8 V V
DD
1.8 V and 1.5 V I/O
165-Bump BGA
Commercial Temp
Industrial Temp
Rev: 1.01 9/2005
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
1/37
2005, GSI Technology
Features
Simultaneous Read and Write SigmaCIO Interface
Common I/O bus
JEDEC-standard pinout and package
Double Data Rate interface
Byte Write (x36 and x18) and Nybble Write (x8) function
Burst of 4 Read and Write
1.8 V +100/–100 mV core power supply
1.5 V or 1.8 V HSTL Interface
Pipelined read operation with self-timed Late Write
Fully coherent read and write pipelines
ZQ pin for programmable output drive strength
IEEE 1149.1 JTAG-compliant Boundary Scan
Pin-compatible with present 9Mb, 18Mb, 36Mb and future
144Mb devices
165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
RoHS-compliant 165-bump BGA package available
SigmaCIO
Family Overview
The GS8662R08/09/18/36E are built in compliance with the
SigmaCIO DDR-II SRAM pinout standard for Common I/O
synchronous SRAMs. They are 75,497,472-bit (72Mb)
SRAMs. The GS8662R08/09/18/36E SigmaCIO SRAMs are
just one element in a family of low power, low voltage HSTL
I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Clocking and Addressing Schemes
The GS8662R08/09/18/36E SigmaCIO DDR-II SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer. The device also allows the user to manipulate the
output register clock inputs quasi independently with the C and
C clock inputs. C and C are also independent single-ended
clock inputs, not differential inputs. If the C clocks are tied
high, the K clocks are routed internally to fire the output
registers instead.
Common I/O x36 and x18 SigmaCIO DDR-II B4
RAMs
always transfer data in four packets. When a new address is
loaded, A0 and A1 preset an internal 2 bit linear address
counter. The counter increments by 1 for each beat of a burst of
four data transfer. The counter always wraps to 00 after
reaching 11, no matter where it starts.
Common I/O x8 SigmaCIO DDR-II B4 RAMs always transfer
data in four packets. When a new address is loaded, the LSBs
are internally set to 0 for the first read or write transfer, and
incremented by 1 for the next 3 transfers. Because the LSBs
are tied off internally, the address field of a x8 SigmaCIO
DDR-II B4 RAM is always two address pins less than the
advertised index depth (e.g., the 4M x 18 has a 1024K
addressable index).
Parameter Synopsis
-333
-300
-250
-200
-167
tKHKH
3.0 ns
3.3 ns
4.0 ns
5.0 ns
6.0 ns
tKHQV
0.45 ns
0.45 ns
0.45 ns
0.45 ns
0.5 ns
165-Bump, 15 mm x 17 mm BGA
1 mm Bump Pitch, 11 x 15 Bump Array
Bottom View
相關PDF資料 |
PDF描述 |
|---|---|
| GS8662R18E-300I | 72Mb SigmaCIO DDR-II Burst of 4 SRAM |
| GS8662R18E-333 | 72Mb SigmaCIO DDR-II Burst of 4 SRAM |
| GS8662R18E-333I | 72Mb SigmaCIO DDR-II Burst of 4 SRAM |
| GS8662R18GE-167 | 72Mb SigmaCIO DDR-II Burst of 4 SRAM |
| GS8662R18GE-167I | 72Mb SigmaCIO DDR-II Burst of 4 SRAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| GS8662R18E-300I | 制造商:GSI Technology 功能描述:SRAM SYNC SGL 1.8V 72MBIT 4MX18 0.45NS 165FBGA - Trays |
| GS8662R18E-333 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb SigmaCIO DDR-II Burst of 4 SRAM |
| GS8662R18E-333I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb SigmaCIO DDR-II Burst of 4 SRAM |
| GS8662R18GE-167 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb SigmaCIO DDR-II Burst of 4 SRAM |
| GS8662R18GE-167I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb SigmaCIO DDR-II Burst of 4 SRAM |
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