- 您現在的位置：買賣IC網 > PDF目錄385338 > GS8662S08E-167I (GSI TECHNOLOGY) 72Mb Burst of 2 DDR SigmaSIO-II SRAM PDF資料下載
參數資料
| 型號： | GS8662S08E-167I |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | 72Mb Burst of 2 DDR SigmaSIO-II SRAM |
| 中文描述： | 8M X 8 DDR SRAM, 0.5 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1 MM PITCH, MO-216CAB-1, FPBGA-165 |
| 文件頁數： | 28/37頁 |
| 文件大小： | 960K |
| 代理商： | GS8662S08E-167I |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁當前第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁
Instruction Register
ID Code Register
·
31 30 29
Boundary Scan Register
0
1
2
0
· · ·
1
2
0
Bypass Register
TDI
TDO
TMS
TCK
Test Access Port (TAP) Controller
1
·
1
0
·
·
·
·
·
·
·
·
·
Control Signals
·
Preliminary
GS8662S08/09/18/36E-333/300/250/200/167
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.01 9/2005
28/37
2005, GSI Technology
JTAG TAP Block Diagram
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
ID Register Contents
Bit #
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
x36
X
X
X
X
0
0
0
0
1
0
0
0
1
0
0
1
0
0
0
0
0
0
0 1 1 0 1 1 0 0 1
1
x18
X
X
X
X
0
0
0
0
1
0
0
0
1
0
0
1
0
0
1
0
0
0
0 1 1 0 1 1 0 0 1
1
x9
X
X
X
X
0
0
0
0
1
0
0
0
1
0
0
1
0
0
1
1
0
0
0 1 1 0 1 1 0 0 1
1
x8
X
X
X
X
0
0
0
0
1
0
0
0
1
0
0
1
0
1
1
1
0
0
0 1 1 0 1 1 0 0 1
1
Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.
相關PDF資料 |
PDF描述 |
|---|---|
| GS8662S08E-200 | 72Mb Burst of 2 DDR SigmaSIO-II SRAM |
| GS8662S08E-200I | 72Mb Burst of 2 DDR SigmaSIO-II SRAM |
| GS8662S08E-250 | 72Mb Burst of 2 DDR SigmaSIO-II SRAM |
| GS8662S08E-250I | 72Mb Burst of 2 DDR SigmaSIO-II SRAM |
| GS8662S08E-300 | 72Mb Burst of 2 DDR SigmaSIO-II SRAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| GS8662S08E-200 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb Burst of 2 DDR SigmaSIO-II SRAM |
| GS8662S08E-200I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb Burst of 2 DDR SigmaSIO-II SRAM |
| GS8662S08E-250 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb Burst of 2 DDR SigmaSIO-II SRAM |
| GS8662S08E-250I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb Burst of 2 DDR SigmaSIO-II SRAM |
| GS8662S08E-300 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb Burst of 2 DDR SigmaSIO-II SRAM |
發布緊急采購，3分鐘左右您將得到回復。