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參數(shù)資料
| 型號： | GS88036AT-150 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs |
| 中文描述： | 為512k × 18，256K × 32，256K × 36 9Mb以上同步突發(fā)靜態(tài)存儲器 |
| 文件頁數(shù)： | 1/26頁 |
| 文件大小： | 756K |
| 代理商： | GS88036AT-150 |
Rev: 1.02 9/2002
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
1/26
2001, Giga Semiconductor, Inc.
GS88018/32/36AT-250/225/200/166/150/133
512K x 18, 256K x 32, 256K x 36
9Mb Sync Burst SRAMs
250 MHz
–
133 MHz
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
100-Pin TQFP
Commercial Temp
Industrial Temp
Features
FT pin for user-configurable flow through or pipeline
operation
Single Cycle Deselect (SCD) operation
2.5 V or 3.3 V +10%/–10% core power supply
2.5 V or 3.3 V I/O supply
LBO pin for Linear or Interleaved Burst mode
Internal input resistors on mode pins allow floating mode pins
Default to Interleaved Pipeline mode
Byte Write (BW) and/or Global Write (GW) operation
Internal self-timed write cycle
Automatic power-down for portable applications
JEDEC-standard 100-lead TQFP package
-250 -225 -200 -166 -150 -133 Unit
Pipeline
3-1-1-1
tCycle
4.0
4.4
Curr
(x18)
Curr
(x32/x36)
330
300
Curr
(x18)
Curr
(x32/x36)
320
295
Flow
Through
2-1-1-1
Curr
(x18)
Curr
(x32/x36)
200
190
Curr
(x18)
Curr
(x32/x36)
200
190
Functional Description
Applications
The GS88018/32/36AT is a 9,437,184-bit (8,388,608-bit for
x32 version) high performance synchronous SRAM with a
2-bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main
store to networking chip set support.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode pin
low places the RAM in Flow Through mode, causing output
data to bypass the Data Output Register. Holding FT high
places the RAM in Pipeline mode, activating the rising-edge-
triggered Data Output Register.
SCD Pipelined Reads
The GS88018/32/36AT is a SCD (Single Cycle Deselect)
pipelined synchronous SRAM. DCD (Dual Cycle Deselect)
versions are also available. SCD SRAMs pipeline deselect
commands one stage less than read commands. SCD RAMs
begin turning off their outputs immediately after the deselect
command has been captured in the input registers.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS88018/32/36AT operates on a 2.5 V or 3.3 V power
supply. All input are 3.3 V and 2.5 V compatible. Separate
output power (V
DDQ
) pins are used to decouple output noise
from the internal circuits and are 3.3 V and 2.5 V compatible.
t
KQ
2.5
2.7
3.0
5.0
230
270
230
265
3.4
6.0
200
230
195
225
3.8
6.7
185
215
180
210
4.0
7.5
165
190
165
185
ns
ns
mA
mA
mA
mA
3.3 V
280
255
2.5 V
275
250
t
KQ
tCycle
5.5
5.5
6.0
6.0
6.5
6.5
7.0
7.0
7.5
7.5
8.5
8.5
ns
ns
3.3 V
175
165
160
180
160
180
150
170
150
170
145
165
145
165
135
150
135
150
mA
mA
mA
mA
2.5 V
175
165
相關PDF資料 |
PDF描述 |
|---|---|
| GS88036AT-150I | 512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs |
| GS88036AT-166 | 512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs |
| GS88036AT-166I | 512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs |
| GS88036AT-200 | 512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs |
| GS88036AT-200I | 512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| GS88036AT-150I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs |
| GS88036AT-166 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs |
| GS88036AT-166I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs |
| GS88036AT-200 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs |
| GS88036AT-200I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs |
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