欧美成人免费电影,国产欧美一区二区三区精品酒店,精品国产a毛片,色网在线免费观看

參數(shù)資料
型號: GS881E36AT-200I
廠商: GSI TECHNOLOGY
元件分類: DRAM
英文描述: 512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs
中文描述: 256K X 36 CACHE SRAM, 6.5 ns, PQFP100
封裝: TQFP-100
文件頁數(shù): 28/37頁
文件大小: 662K
代理商: GS881E36AT-200I
GS881E18/36AT-250/225/200/166/150/133
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03 11/2004
20/29
2001, GSI Technology
JTAG Port Registers
Overview
The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s
and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the
rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the
TDI and TDO pins.
Instruction Register
The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.
Bypass Register
The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through
the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
JTAG Pin Descriptions
Pin
Pin Name
I/O
Description
TCK
Test Clock
In
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate
from the falling edge of TCK.
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP
controller state machine. An undriven TMS input will produce the same result as a logic one input
level.
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers
placed between TDI and TDO. The register placed between TDI and TDO is determined by the
state of the TAP Controller state machine and the instruction that is currently loaded in the TAP
Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce
the same result as a logic one input level.
Output that is active depending on the state of the TAP state machine. Output changes in
response to the falling edge of TCK. This is the output side of the serial registers placed between
TDI and TDO.
TMS
Test Mode Select
In
TDI
Test Data In
In
TDO
Test Data Out
Out
Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.
相關(guān)PDF資料
PDF描述
GS881E36AT-200IT 512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs
GS881E36AT-200T 512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs
GS881E36AT-225 512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs
GS881E36AT-225I 512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs
GS881E36AT-225IT 512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS881E36AT-200IT 制造商:GSI 制造商全稱:GSI Technology 功能描述:512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs
GS881E36AT-200T 制造商:GSI 制造商全稱:GSI Technology 功能描述:512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs
GS881E36AT-225 制造商:GSI 制造商全稱:GSI Technology 功能描述:512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs
GS881E36AT-225I 制造商:GSI 制造商全稱:GSI Technology 功能描述:512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs
GS881E36AT-225IT 制造商:GSI 制造商全稱:GSI Technology 功能描述:512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs
主站蜘蛛池模板: 宜兴市| 田林县| 永福县| 乌兰浩特市| 舞钢市| 都江堰市| 土默特右旗| 巫山县| 西充县| 邵阳县| 上高县| 东明县| 泰和县| 视频| 花莲县| 蕲春县| 明星| 九龙县| 正蓝旗| 扎囊县| 海伦市| 上思县| 临沧市| 邢台市| 霍州市| 万宁市| 崇左市| 新龙县| 辰溪县| 富川| 大厂| 白水县| 潜江市| 贺州市| 蚌埠市| 五原县| 钟祥市| 洪泽县| 平安县| 宣汉县| 柳林县|