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參數資料
| 型號： | GS881Z18T-100I |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | 8Mb Pipelined and Flow Through Synchronous NBT SRAMs |
| 中文描述： | 512K X 18 ZBT SRAM, 12 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數： | 28/34頁 |
| 文件大小： | 542K |
| 代理商： | GS881Z18T-100I |
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Rev: 1.10 8/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
28/34
1998, Giga Semconductor, Inc.
Preliminary
.
GS881Z18/36T-11/100/80/66
JTAG Port Recommended Operating Conditions and DC Characteristics
JTAG Port AC Test Conditions
Parameter
Symbol Mn.
V
IHT
V
ILT
I
INTH
I
INTL
I
OLT
V
OHT
V
OLT
Max.
V
DD
+0.3
Unit Notes
Test Port Input High Voltage
1.7
V
1, 2
Test Port Input Low Voltage
–0.3
0.8
V
1, 2
TMS, TCK and TDI Input Leakage Current
–300
1
uA
3
TMS, TCK and TDI Input Leakage Current
–1
1
uA
4
TDO Output Leakage Current
–1
1
uA
5
Test Port Output High Voltage
2.4
—
V
6, 7
Test Port Output Low Voltage
—
0.4
V
6, 8
Notes:
1.
2.
This device features input buffers compatible with both 3.3 V and 2.5 V I/O drivers.
Input Under/overshoot voltage must be –2 V > Vi < V
DD
+2 V with a pulse width not to exceed 20%
tTKC.
V
DD
≥
V
IN
≥
V
IL
0 V
≤
V
IN
≤
V
IL
Output Disable, V
OUT
= 0 to V
DD
The TDO output driver is served by the V
DD
supply.
I
OH
= –4 mA
I
OL
= +4 mA
3.
4.
5.
6.
7.
8.
Notes:
1.
Include scope and jig capacitance.
Parameter
Input high level
Input low level
Input slew rate
Input reference level
Output reference level
Conditions
2.3 V
0.2 V
1 V/ns
1.25 V
1.25 V
DQ
V
T
= 1.25 V
50
30pF
*
JTAG Port AC Test Load
*Distributed Test Jig Capacitance
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