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參數資料
| 型號： | GS881Z18T-80 |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | 8Mb Pipelined and Flow Through Synchronous NBT SRAMs |
| 中文描述： | 512K X 18 ZBT SRAM, 14 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數： | 4/34頁 |
| 文件大小： | 542K |
| 代理商： | GS881Z18T-80 |
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Rev: 1.10 8/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
4/34
1998, Giga Semconductor, Inc.
Preliminary
.
GS881Z18/36T-11/100/80/66
100-Pin TQFP Pin Descriptions
Pin Location
37, 36
35, 34, 33, 32, 100, 99, 83, 82,
81, 50, 49, 48, 47, 46, 45, 44
80
89
93
94
95
96
88
98
97
92
86
85
87
58, 59, 62,63, 68, 69, 72, 73, 74
8, 9, 12, 13, 18, 19, 22, 23, 24
51, 52, 53, 56, 57, 75, 78, 79,
1, 2, 3, 6, 7, 25, 28, 29, 30
51, 52, 53, 56, 57, 58, 59, 62,63
68, 69, 72, 73, 74, 75, 78, 79, 80 DQ
B1
–DQ
B9
1, 2, 3, 6, 7, 8, 9, 12, 13
18, 19, 22, 23, 24, 25, 28, 29, 30 DQ
D1
–DQ
D9
64
14
31
Symbol
A
0
, A
1
Type
In
Description
Burst Address Inputs—Preload the burst counter
A
2
–A
17
In
Address Inputs
A
18
CK
B
A
B
B
B
C
B
D
W
E
1
E
2
E
3
G
ADV
CKE
In
In
In
In
In
In
In
In
In
In
In
In
In
I/O
I/O
Address Input (x18 Version Only)
Clock Input Signal
Byte Write signal for data inputs DQ
A1
–DQ
A9
; active low
Byte Write signal for data inputs DQ
B1
–DQ
B9
; active low
Byte Write signal for data inputs DQ
C1
–DQ
C9
; active low (x36 Version Only)
Byte Write signal for data inputs DQ
D1
–DQ
D9
; active low (x36 Version Only)
Write Enable; active low
Chip Enable; active low
Chip Enable; active high; for self decoded depth expansion
Chip Enable; active low; for self decoded depth expansion
Output Enable; active low
Advance/Load—Burst address counter control pin
Clock Input Buffer Enable; active low
Byte A Data Input and Output pins (x18 Version Only)
Byte B Data Input and Output pins (x18 Version Only)
DQ
A1
–DQ
A9
DQ
B1
–DQ
B9
NC
—
No Connect (x18 Version Only)
DQ
A1
–DQ
A9
I/O
I/O
I/O
I/O
In
In
In
Byte A Data Input and Output pins (x36 Versions Only)
Byte B Data Input and Output pins (x36 Versions Only)
Byte C Data Input and Output pins (x36 Versions Only)
Byte D Data Input and Output pins (x36 Versions Only)
Power down control; active high
Pipeline/Flow Through Mode Control; active low
Linear Burst Order; active low
DQ
C1
–DQ
C9
ZZ
FT
LBO
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