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參數資料
| 型號： | GS88218BB-333 |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | 512K x 18, 256K x 36 9Mb SCD/DCD Sync Burst SRAMs |
| 中文描述： | 512K X 18 CACHE SRAM, 4.5 ns, PBGA119 |
| 封裝： | FPBGA-119 |
| 文件頁數： | 30/37頁 |
| 文件大小： | 751K |
| 代理商： | GS88218BB-333 |
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GS88218/36BB/D-333/300/250/200/150
Rev: 1.02 10/2004
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
30/37
2002, GSI Technology
JTAG Port AC Test Conditions
JTAG TAP Instruction Set Summary
Instruction
Code
Description
Notes
EXTEST
000
Places the Boundary Scan Register between TDI and TDO.
1
IDCODE
001
Preloads ID Register and places it between TDI and TDO.
1, 2
SAMPLE-Z
010
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
Forces all RAM output drivers to High-Z.
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
1
RFU
011
1
SAMPLE/
PRELOAD
100
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
1
GSI
101
GSI private instruction.
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
1
RFU
110
1
BYPASS
111
Places Bypass Register between TDI and TDO.
1
Notes:
1.
2.
Instruction codes expressed in binary, MSB on left, LSB on right.
Default instruction automatically loaded at power-up and in test-logic-reset state.
Notes:
1.
2.
Include scope and jig capacitance.
Test conditions as shown unless otherwise noted.
Parameter
Conditions
V
DD
– 0.2 V
0.2 V
1 V/ns
V
DDQ
/2
V
DDQ
/2
Input high level
Input low level
Input slew rate
Input reference level
Output reference level
DQ
V
DDQ
/2
50
30pF
*
JTAG Port AC Test Load
* Distributed Test Jig Capacitance
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相關代理商/技術參數 |
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| GS88218CB-200 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 9MBIT 512KX18 6.5NS/3NS 119FPBGA - Trays |
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| GS88218CB-200V | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V/2.5V 9MBIT 512KX18 6.5NS/3NS 119FPBGA - Trays |
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