- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385342 > GS88236BD-150I (GSI TECHNOLOGY) 512K x 18, 256K x 36 9Mb SCD/DCD Sync Burst SRAMs PDF資料下載
參數(shù)資料
| 型號： | GS88236BD-150I |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | 512K x 18, 256K x 36 9Mb SCD/DCD Sync Burst SRAMs |
| 中文描述： | 256K X 36 CACHE SRAM, 7.5 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1 MM PITCH, FPBGA-165 |
| 文件頁數(shù)： | 25/37頁 |
| 文件大小： | 751K |
| 代理商： | GS88236BD-150I |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁當前第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁
GS88218/36BB/D-333/300/250/200/150
Rev: 1.02 10/2004
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
25/37
2002, GSI Technology
JTAG Port Registers
JTAG Pin Descriptions
Overview
The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s
and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the
rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the
TDI and TDO pins.
Instruction Register
The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.
Bypass Register
The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through
the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
Pin
Pin Name
I/O
Description
TCK
Test Clock
In
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate
from the falling edge of TCK.
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP
controller state machine. An undriven TMS input will produce the same result as a logic one input
level.
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers
placed between TDI and TDO. The register placed between TDI and TDO is determined by the
state of the TAP Controller state machine and the instruction that is currently loaded in the TAP
Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce
the same result as a logic one input level.
Output that is active depending on the state of the TAP state machine. Output changes in
response to the falling edge of TCK. This is the output side of the serial registers placed between
TDI and TDO.
TMS
Test Mode Select
In
TDI
Test Data In
In
TDO
Test Data Out
Out
Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS88236BD-200 | 512K x 18, 256K x 36 9Mb SCD/DCD Sync Burst SRAMs |
| GS88236BD-200I | 512K x 18, 256K x 36 9Mb SCD/DCD Sync Burst SRAMs |
| GS88236BD-250 | 512K x 18, 256K x 36 9Mb SCD/DCD Sync Burst SRAMs |
| GS88236BD-250I | 512K x 18, 256K x 36 9Mb SCD/DCD Sync Burst SRAMs |
| GS88236BD-300 | 512K x 18, 256K x 36 9Mb SCD/DCD Sync Burst SRAMs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS88236CB-200 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 9MBIT 256KX36 6.5NS/3NS 119FPBGA - Trays |
| GS88236CB-200I | 制造商:GSI Technology 功能描述:256K X 36 (9 MEG) SYNCH BURST , SCD, JTAG, FLEXDRIVE - Trays |
| GS88236CB-200IV | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V/2.5V 9MBIT 256KX36 6.5NS/3NS 119FPBGA - Trays |
| GS88236CB-250 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 9MBIT 256KX36 5.5NS/2.5NS 119FPBGA - Trays |
| GS88236CD-200 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 9MBIT 256KX36 6.5NS/3NS 165FPBGA - Trays |
發(fā)布緊急采購，3分鐘左右您將得到回復。