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參數(shù)資料
型號(hào): GS88237BD-300I
廠商: GSI TECHNOLOGY
元件分類: DRAM
英文描述: 256K x 36 9Mb SCD/DCD Sync Burst SRAM
中文描述: 256K X 36 CACHE SRAM, 2.2 ns, PBGA165
封裝: 13 X 15 MM, 1 MM PITCH, FBGA-165
文件頁(yè)數(shù): 18/29頁(yè)
文件大小: 577K
代理商: GS88237BD-300I
GS88237BB/D-333/300/250/200
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04 3/2005
18/29
2002, GSI Technology
JTAG TAP Block Diagram
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
Instruction Register
ID Code Register
·
31 30 29
Boundary Scan Register
0
1
2
0
· · ·
1
2
0
Bypass Register
TDI
TDO
TMS
TCK
Test Access Port (TAP) Controller
1
·
1
0
·
·
·
·
·
·
·
·
·
Control Signals
·
相關(guān)PDF資料
PDF描述
GS88237BD-333 256K x 36 9Mb SCD/DCD Sync Burst SRAM
GS88237BD-333I 256K x 36 9Mb SCD/DCD Sync Burst SRAM
GS88237BGB-200 256K x 36 9Mb SCD/DCD Sync Burst SRAM
GS88237BGB-200I 256K x 36 9Mb SCD/DCD Sync Burst SRAM
GS88237BGB-250 256K x 36 9Mb SCD/DCD Sync Burst SRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS88237CB-200 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 9MBIT 256KX36 2.7NS 119FPBGA - Trays
GS88237CB-200I 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 9MBIT 256KX36 2.7NS 119FPBGA - Trays
GS88237CB-200IV 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V/2.5V 9MBIT 256KX36 2.5NS 119FPBGA - Trays
GS88237CB-200V 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V/2.5V 9MBIT 256KX36 2.5NS 119FPBGA - Trays
GS88237CB-250 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 9MBIT 256KX36 2.3NS 119FPBGA - Trays
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