
GENLINX
GS9002A
Serial Digital Encoder
DATA SHEET
FEATURES
DEVICE DESCRIPTION
The GS9002A is a monolithic bipolar integrated circuit
designed to serialize SMPTE 125M and SMPTE 244M bit
parallel digital signals as well as other 8 or 10 bit parallel
formats. This device performs the functions of sync detection,
parallel to serial conversion, data scrambling (using the X
9
+
X
4
+1 algorithm), 10x parallel clock multiplication and
conversion of NRZ to NRZI serial data. It supports any of four
selectable serial data rates from 100 Mb/s to over 360 Mb/s.
The data rates are set by resistors and are selected by an
on-board 2:4 decoder having two TTL level input address
lines.
Other features such as a sync detector output, a sync detector
disable input, and a lock detect output are also provided. The
X
9
+ X
4
+ 1 scrambler and NRZ to NRZI converter may be
bypassed to allow the output of the parallel to serial converter
to be directly routed to the output drivers.
The GS9002A provides pseudo-ECL outputs for the serial
data and serial clock as well as a single-ended pseudo-ECL
output of the regenerated parallel clock.
The GS9002A directly interfaces with cable drivers GS9007A,
GS9008A and GS9009A. The device requires a single +5 volt
or -5 volt supply and typically consumes 713 mW of power
while driving 100
loads. The 44 pin PLCC packaging
assures a small footprint for the complete encoder function.
fully compatible with SMPTE-259M serial digital
standard
supports up to four serial bit rates to 400 Mb/s
accepts 8 bit and 10 bit TTL and CMOS
compatible parallel data inputs
X
9
+ X
4
+ 1 scrambler, NRZI converter and sync
detector may be disabled for transparent data
transmission
pseudo-ECL serial data and clock outputs
single +5 or -5 volt supply
713 mW typical power dissipation (including ECL
pull-down loads).
44 pin PLCC packaging
Pb-free and Green
APPLICATIONS
4
SC
, 4:2:2 and 360 Mb/s serial digital interfaces for
Video cameras, VTRs, Signal generators
ORDERING INFORMATION
Revision Date: June 2004
FUNCTIONAL BLOCK DIAGRAM
Patent No.5,357,220
GENNUM CORPORATION P.O. Box 489, Stn A, Burlington, Ontario, Canada L7R 3Y3 tel. (905) 632-2996 fax: (905) 632-5946
Gennum Japan: Shinjuku Green Tower Building 27F 6-14-1, Nishi Shinjuku Shinjuku-ku, Tokyo 160-0023 Japan Tel: +81 (03) 3349-5501 Fax: +81 (03) 3349-5505
Document No. 24149 - 1
SYNC DETECT
DISABLE
GS9002A
PLD
LOOP FILTER
RVC00
RVC01
RVC02
RVC03
LOCK DETECT
SERIAL CLOCK
SYNC DETECT
PCLK IN
PARALLEL DATA
IN (10 BITS)
P/S
CONVERTER
PCLK OUT
DRS1
DRS0
SYNC
DETECT
DATA RATE
SWITCH
REGULATOR CAP
PHASE
FREQUENCY
DETECT
CHARGE
PUMP
VCO
INPUT
LATCH
DIV BY 10
GENERATOR
6
7-16
17
22
19
3
20
43
29
36
32
31
33
35
34
26
SCRAMBLER/
SERIALIZER
SELECT
SCLK
LOCK
DETECT
NRZ
NRZI
2:1 MUX
SERIAL CLOCK
42
SCRAMBLER
SERIAL DATA
SERIAL DATA
39
38
N
GS9002ACPM
44 Pin PLCC
o°C to 70°C
No
GS9002ACPME3
44 Pin PLCC
o°C to 70°C
Yes