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參數資料
| 型號： | GS9025 |
| 英文描述： | GENLINX II Serial Digital Receiver |
| 中文描述： | GENLINX二串行數字接收機 |
| 文件頁數： | 1/30頁 |
| 文件大?。?/td> | 445K |
| 代理商： | GS9025 |
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GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: info@gennum.com
www.gennum.com
Revision Date: March 2002
Document No. 19922 - 2
DATA SHEET
G
FEATURES
fully compatible with SMPTE 259M
drop-in replacement for the GS9020
auto-standard operation to 540MHz
embedded EDH and data processing core
selectable loop through or re-serialized EDH-processed
serial output
noise immune HVF timing signal outputs
configurable FIFO reset pulse for clearing downstream
FIFOs
ANC header and TRS-ID correction for all standards
user controlled output blanking
ITU-R-601 output clipping for active picture area
ancillary data indication
low system power
selectable I2C interface or 8-bit parallel port for access to
EDH flags and device configuration bits
EDH flags also available on dedicated pins
seamless flag mapping to GS9021 EDH coprocessor
80 pin LQFP
APPLICATIONS
SMPTE 259M serial digital receiver for composite and
component standards including 4:4:4:4 at 540Mb/s with
EDH processing; Noise immune digital sync and timing
generation; Cost effective EDH insertion and checking for
serial routing and distribution applications.
DESCRIPTION
The GS9020A is specifically designed to deserialize SMPTE
259M serial digital signals. The inclusion of Error Detection
and Handling (EDH) ensures the integrity of the data being
received from the serial digital interface (SDI). Internal 75
termination
resistors
allow
connection with the GS9035A Reclocker or the GS9025A
Receiver, thus providing a complete high performance,
digital video input processor with EDH, digital sync signal
generation, and other system features.
INTERLINX
seamless
The GS9020A also includes a parallel to serial converter
and NRZI scrambler to provide re-serialized, EDH
compliant data output. The EDH core implements EDH
insertion and extraction according to SMPTE RP-165. This
core also generates noise immune timing signals such as
horizontal sync, vertical blanking, field ID and ancillary data
identification. It also provides many system features such
as a FIFO reset pulse (which can be programmed to
coincide with either EAV or SAV), TRS-ID and ANC header
correction, user controlled output blanking and ITU-R-601
output clipping. The GS9020A has an I2C (Inter-Integrated
Circuit, I2C is a registered Trademark of Philips) serial
interface bus and an 8-bit parallel port for external access
to all error flags and device configuration bits.
BLOCK DIAGRAM
ORDERING INFORMATION
PART NUMBER
PACKAGE
TEMPERATURE
GS9020ACFV
80 pin LQFP Tray
0°C to 70°C
GS9020ACTV
80 pin LQFP Tape
0°C to 70°C
DOUT[9:0]
FIFO_RESET
HVF
CLIP_TRS
HOSTIF
STANDARDS
INDICATOR
PCLK OUT
FRAMED
DATA [9:0]
SDOMODE
PCLKOUT
SDO
SDO
SDI
SDI
SCI
SCI
RESET
EDH
AND DATA
PROCESSING
CORE
ALIGNING
CONTROL
UNIT
10
10
7
TRS_ERR
PRESCALER
DEDICATED
FLAG PORT
ANC_CHKSM
BUF
0
1
BUF
BUF
SERIAL TO
PARALLEL
CONVERTER
PARALLEL TO
SERIAL
CONVERTER
WITH SCRAMBLER
DESCRAMBLER
SYNC
DETECTOR
5
4
GS9020A
Serial Digital Video Input Processor
相關PDF資料 |
PDF描述 |
|---|---|
| GS9032 | 143-540Mb/s Serializer for SDI and DVB-ASI. |
| GS9032-CTM | SMPTE |
| GS9032-CVM | SMPTE |
| GS9035 | GENLINX II Serial Digital Reclocker |
| GS9035C | 143-360Mb/s Reclocker. |
相關代理商/技術參數 |
參數描述 |
|---|---|
| GS9025 44PQFP | 制造商:Gennum Corporation 功能描述: |
| GS9025A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Serial Digital Receiver |
| GS9025A_05 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:Serial Digital Receiver |
| GS9025ACQM | 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述: |
| GS9025ACQME3 | 制造商:Semtech Corporation 功能描述:Cable Equalization 44-Pin MQFP Tray 制造商:Semtech Corporation 功能描述:GS9025 Series 540 Mb/s Cable Equalization Serial Digital Receiver - MQFP-44 制造商:Semtech Corporation 功能描述:Receiver |
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