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| 型號(hào)： | GT-64111 |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | System Controller for RC4640, RM523X and VR4300 CPUs(用于RC4640, RM523X和 VR4300 CPUs的系統(tǒng)控制器) |
| 中文描述： | 系統(tǒng)控制器（用于RC4640，RM523X和VR4300處理器的系統(tǒng)控制器的RC4640，RM523X和VR4300處理器） |
| 文件頁(yè)數(shù)： | 1/130頁(yè) |
| 文件大小： | 881K |
| 代理商： | GT-64111 |
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GT-64111
System Controller for RC4640,
RM523X and VR4300 CPUs
Product Preview
Revision 1.1
FEB 4, 1999
Please contact Galileo Technology for possible
updates before finalizing a design.
FEATURES
www.galileoT.com
support@galileoT.com
Tel: +1-408.367.1400
Fax: +1-408.367.1401
Integrated PCI system controller for high-performance
cost sensitive embedded applications
Support the following 32-bit bus CPUs:
- IDT RC4640 and RC4650 (in 32-bit mode)
- QED RM523X
- NEC/Toshiba VR4300
Up to 66MHz CPU bus frequency
64 byte CPU write posting buffer
- 32-bit wide, 16 levels deep
- Accepts CPU writes with zero wait-states
EDO and Fast Page Mode DRAM controller
- 512MB address space
- Supports DRAM bank interleaving
- 256KB-16MB device depth
- 1- 4 banks supported
- 32-bit or 64-bit data width
- Parity supported
- Zero wait-state interleaved burst accesses at
66MHz
Device controller
- 5 chip selects
- Programmable timing for each chip select
- Supports many types of standard memory and I/O
devices
- Up to 160MB address space
- Optional external wait-state support
- 8-,16-,32- and 64-bit width device support
- Support for boot ROMs
- Parity supported for devices
Four channel DMA controller
- Chaining via linked-lists of records
- Byte alignment on source and destination
- Transfers through 32-byte internal FIFO
- Moves data between PCI, memory, and devices
High-performance 32-bit Universal PCI 2.1 interface
- 96-bytes of posted write and read prefetch buffers
- 32-bit PCI master and target operations
- PCI bus speed of up to 66MHz with no wait states
- Operates either synchronous or asynchronous to
CPU clock
- Burst transfers used for efficient data movement
- Doorbell interrupts provided between CPU and PCI
- Supports flexible byte swapping through PCI inter-
face
- Synchronization barrier support
- PCI configuration registers can be accessed from
both CPU and PCI side
- Support for both 5V and 3.3V operation
Host to PCI bridge
- Translates CPU cycles into PCI I/O or Memory
cycles
- Generates PCI Configuration, Interrupt Acknowl-
edge, and Special cycles on PCI bus
PCI to Main Memory bridge
- Supports fast back-to-back transactions
- Supports memory and I/O transactions to internal
configuration registers
- Supports locked operations
Three 24-bit wide and one 32-bit wide timer/counters
Plug and Play Support
- PC compatible configuration registers
- PCI configuration header can be loaded from boot
PROM
- PCI configuration registers are accessed from both
CPU and PCI bus
3.3V Supply Voltage (PCI and Peripherals)
- 5V tolerant I/Os
208 PQFP
GT-64111
32-bit/66MHz SysAD
CPU
32-bit/66MHz PCI Bus
Network
Other
. . .
SCSI
32-bit Address/Data Bus
Address/Control
Flash
I/O
. . .
SDRAM
相關(guān)PDF資料 |
PDF描述 |
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| GT-96100A | Advanced Communication Controller That Handles a Wide Range of Serial Communication Protocols,such as Ethernet,Fast Ethernet,and HDLC(通信協(xié)議的高級(jí)通信協(xié)議（以太網(wǎng)、快速以太網(wǎng)、HDLC）控制器) |
| GT5-2/1S-HU | RECTANGULAR CONNECTOR |
| GT5-1S-HU(A) | RECTANGULAR CONNECTOR |
| GT5-1S-HU(B) | RECTANGULAR CONNECTOR |
| GT5-2S-HU | RECTANGULAR CONNECTOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GT64115-A2-PBB-C000 | 制造商:Marvell 功能描述: 制造商:Marvell 功能描述:Marvell GT64115-A2-PBB-C000 |
| GT-64120A-B-0 | 制造商:GALILEO 功能描述: |
| GT-64120A-B2 | 制造商:GALILEO 功能描述:MULTIFUNCTION PERIPHERAL, 388 Pin Plastic BGA 制造商:Galileo Corp 功能描述:MULTIFUNCTION PERIPHERAL, 388 Pin Plastic BGA 制造商:Marvell 功能描述:MULTIFUNCTION PERIPHERAL, 388 Pin Plastic BGA |
| GT64120AB2-BBB1C000 | 制造商:Marvell 功能描述:64-BIT MIPS SYSTEM CONTROLLER W/ 2 X 32-BIT OR 1 X 64-BIT/6 - Trays |
| GT64120AB2-BBB1C083 | 制造商:Marvell 功能描述:Marvell GT64120AB2-BBB1C083 |
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