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參數資料
| 型號： | GTL2003PW |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 電壓/頻率轉換 |
| 英文描述： | 8-bit bidirectional low voltage translator |
| 封裝： | GTL2003BQ<SOT764-1 (DHVQFN20)|<<http://www.nxp.com/packages/SOT764-1.html<1<Always Pb-free,;GTL2003PW<SOT360-1 (TSSOP20)|<<http://www.nxp.com/packages/SOT360-1.html<1& |
| 文件頁數： | 6/19頁 |
| 文件大小： | 113K |
| 代理商： | GTL2003PW |
GTL2003_1
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 27 July 2007
6 of 19
NXP Semiconductors
GTL2003
8-bit bidirectional low voltage translator
8.2 Unidirectional down translation
For unidirectional clamping, higher voltage to lower voltage, the GREF input must be
connected to DREF and both pins pulled to the higher side V
CC
through a pull-up resistor
(typically 200 k
). A filter capacitor on DREF is recommended. Pull-up resistors are
required if the chip set I/O are open-drain. The opposite side of the reference transistor
(SREF) is connected to the processor core supply voltage. When DREF is connected
through a 200 k
resistor to a 3.3 V to 5.5 V V
CC
supply and SREF is set between 1.0 V
to (V
CC
1.5 V), the output of each Sn has a maximum output voltage equal to SREF.
8.3 Unidirectional up translation
For unidirectional up translation, lower voltage to higher voltage, the reference transistor is
connected the same as for a down translation. A pull-up resistor is required on the higher
voltage side (Dn or Sn) to get the full HIGH level, since the GTL-TVC device will only pass
the reference source (SREF) voltage as a HIGH when doing an up translation. The driver
on the lower voltage side only needs pull-up resistors if it is open-drain.
Typical unidirectional HIGH-to-LOW voltage translation.
Fig 5.
Unidirectional down translation to protect low voltage processor pins
GREF
DREF
002aac061
D1
D2
200 k
GTL2002
CHIPSET I/O
V
CC
5 V
GND
SREF
S1
S2
CPU I/O
V
CORE
1.8 V
1.5 V
1.2 V
1.0 V
totem pole I/O
easy migration to lower voltage
as processor geometry shrinks
Typical unidirectional LOW-to-HIGH voltage translation.
Fig 6.
Unidirectional down translation to protect low voltage processor pins
GREF
DREF
002aac062
D1
D2
200 k
GTL2002
CHIPSET I/O
V
CC
5 V
GND
SREF
S1
S2
CPU I/O
V
CORE
1.8 V
1.5 V
1.2 V
1.0 V
easy migration to lower voltage
as processor geometry shrinks
totem pole I/O
or open-drain
相關PDF資料 |
PDF描述 |
|---|---|
| GTL2005PW | Quad GTL-GTL+ to LVTTL-TTL bidirectional non-latched translator |
| GTL2006PW | 13-bit GTL--GTL-GTL+ to LVTTL translator |
| GTL2007PW | 12-bit GTL to LVTTL translator with power good control |
| GTL2008PW | 12-bit GTL to LVTTL translator with power good control and high-impedance LVTTL and GTL outputs |
| GTL2010BS | 10-bit bidirectional low voltage translator |
相關代理商/技術參數 |
參數描述 |
|---|---|
| GTL2003PW,112 | 功能描述:轉換 - 電壓電平 8-BIT GTL VOLTAGE RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8 |
| GTL2003PW,118 | 功能描述:轉換 - 電壓電平 8-BIT GTL VOLTAGE RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8 |
| GTL2003PW,118-CUT TAPE | 制造商:NXP 功能描述:GTL2003 Series I2C 8-Bit Bidirectional Low Voltage Translator - TSSOP - 20 |
| GTL2003PW-T | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:NXP bidirectional low-voltage translators |
| GTL2004 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Quad GTL/GTL to LVTTL/TTL bidirectional latched translator |
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