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參數資料
| 型號： | GTL2010PW |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 電壓/頻率轉換 |
| 英文描述： | 10-bit bidirectional low voltage translator |
| 封裝： | GTL2010BS<SOT616-1 (HVQFN24)|<<http://www.nxp.com/packages/SOT616-1.html<1<Always Pb-free,;GTL2010PW<SOT355-1 (TSSOP24)|<<http://www.nxp.com/packages/SOT355-1.html<1&l |
| 文件頁數： | 6/20頁 |
| 文件大小： | 117K |
| 代理商： | GTL2010PW |
GTL2010_6
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 3 March 2008
6 of 20
NXP Semiconductors
GTL2010
10-bit bidirectional low voltage translator
8.2 Unidirectional down translation
For unidirectional clamping, higher voltage to lower voltage, the GREF input must be
connected to DREF and both pins pulled to the higher side V
CC
through a pull-up resistor
(typically 200 k
). A filter capacitor on DREF is recommended. Pull-up resistors are
required if the chip set I/Os are open-drain. The opposite side of the reference transistor
(SREF) is connected to the processor core supply voltage. When DREF is connected
through a 200 k
resistor to a 3.3 V to 5.5 V V
CC
supply and SREF is set between 1.0 V
to (V
CC
1.5 V), the output of each Sn has a maximum output voltage equal to SREF.
8.3 Unidirectional up translation
For unidirectional up translation, lower voltage to higher voltage, the reference transistor is
connected the same as for a down translation. A pull-up resistor is required on the higher
voltage side (Dn or Sn) to get the full HIGH level, since the GTL-TVC device will only pass
the reference source (SREF) voltage as a HIGH when doing an up translation. The driver
on the lower voltage side only needs pull-up resistors if it is open-drain.
Typical unidirectional HIGH-to-LOW voltage translation.
Fig 5.
Unidirectional down translation to protect low voltage processor pins
GREF
DREF
002aac061
D1
D2
200 k
CHIPSET I/O
V
CC
5 V
GND
SREF
S1
S2
CPU I/O
V
CORE
1.8 V
1.5 V
1.2 V
1.0 V
totem pole I/O
easy migration to lower voltage
as processor geometry shrinks
Typical unidirectional LOW-to-HIGH voltage translation.
Fig 6.
Unidirectional down translation to protect low voltage processor pins
GREF
DREF
002aac062
D1
D2
200 k
CHIPSET I/O
V
CC
5 V
GND
SREF
S1
S2
CPU I/O
V
CORE
1.8 V
1.5 V
1.2 V
1.0 V
easy migration to lower voltage
as processor geometry shrinks
totem pole I/O
or open-drain
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相關代理商/技術參數 |
參數描述 |
|---|---|
| GTL2010PW,112 | 功能描述:轉換 - 電壓電平 1-BIT GTL VOLTAGE CLAMP TRANS RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8 |
| GTL2010PW,118 | 功能描述:轉換 - 電壓電平 1-BIT GTL VOLTAGE RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8 |
| GTL2010PW/G,118 | 功能描述:IC VOLT TRANSLATOR 24-TSSOP RoHS:是 類別:集成電路 (IC) >> 邏輯 - 變換器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:100 系列:- 邏輯功能:變換器，雙向 位數:2 輸入類型:CMOS 輸出類型:CMOS 數據速率:16Mbps 通道數:2 輸出/通道數目:1 差分 - 輸入:輸出:無/無 傳輸延遲（最大）:15ns 電源電壓:1.65 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:10-UFQFN 供應商設備封裝:10-UTQFN（1.4x1.8） 包裝:管件 |
| GTL2010PW/N,118 | 功能描述:轉換 - 電壓電平 1-BIT GTL VOLTAGE RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8 |
| GTL2010PW/N-T | 功能描述:轉換 - 電壓電平 1-BIT GTL VOLTAGE CLAMP TRANS RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8 |
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