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參數資料
| 型號： | GTLP36T612GX |
| 英文描述： | 18-Bit Bus Transceiver |
| 中文描述： | 18位總線收發器 |
| 文件頁數： | 1/8頁 |
| 文件大小： | 78K |
| 代理商： | GTLP36T612GX |
2001 Fairchild Semiconductor Corporation
DS500590
www.fairchildsemi.com
September 2001
Revised September 2001
G
GTLP36T612
36-Bit LVTTL/GTLP Universal Bus Transceiver
General Description
The GTLP36T612 is an 36-bit universal bus transceiver
which provides LVTTL to GTLP signal level translation. It
allows for transparent, latched and clocked modes of data
transfer. The device provides a high speed interface for
cards operating at LVTTL logic levels and a backplane
operating at GTLP logic levels. High speed backplane
operation is a direct result of GTLP’s reduced output swing
(
<
1V), reduced input threshold levels and output edge rate
control. The edge rate control minimizes bus settling time.
GTLP is a Fairchild Semiconductor derivative of the Gun-
ning Transistor logic (GTL) JEDEC standard JESD8-3.
Fairchild’s GTLP has internal edge-rate control and is Pro-
cess, Voltage, and Temperature (PVT) compensated. Its
function is similar to BTL or GTL but with different output
levels and receiver thresholds. GTLP output LOW level is
less than 0.5V, the output HIGH is 1.5V and the receiver
threshold is 1.0V.
Features
I
Bidirectional interface between GTLP and LVTTL logic
levels
I
Designed with edge rate control circuitry to reduce out-
put noise on the GTLP port
I
Partitioned as two 18-Bit transceivers with individual
latch timing and output control
I
V
REF
pin provides external supply reference voltage for
receiver threshold adjustibility
I
Special PVT compensation circuitry to provide consis-
tent performance over variations of process, supply volt-
age and temperature
I
TTL compatible driver and control inputs
I
Designed using Fairchild advanced BiCMOS technology
I
Bushold data inputs on A port to eliminate the need for
external pull-up resistors for unused inputs
I
Power up/down and power off high impedance for live
insertion
I
Open drain on GTLP to support wired-or connection
I
Flow through pinout optimizes PCB layout
I
D-type flip-flop, latch and transparent data paths
I
A Port source/sink
24mA/
+
24mA
I
B Port sink
+
50mA
I
For more information see AN-5026,
Using BGA Packages
Ordering Code:
Note 1:
BGA package available in Tape and Reel only.
Order Number
GTLP36T612GX
(Note 1)
Package Number
BGA114A
Package Description
114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[TAPE and REEL]
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