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參數資料
| 型號： | GVT72512A8J-15L |
| 英文描述： | x8 SRAM |
| 中文描述： | x8的SRAM |
| 文件頁數： | 1/9頁 |
| 文件大?。?/td> | 64K |
| 代理商： | GVT72512A8J-15L |
ASYNCHRONOUS
SRAM
512K x 8 SRAM
+5V SUPPLY
REVOLUTIONARY PINOUT
GVT72512A8
REVOLUTIONARY PINOUT 512K X 8
GALVANTECH
, INC.
Galvantech, Inc. reserves the right to chang
products or specifications without notice
Rev. 1/99
Galvantech, Inc. 3080 Oakmead Village Drive, Santa Clara, CA 95051
Tel (408) 566-0688
Fax (408) 566-0699
Web Site http://www.galvantech.com
FEATURES
Fast access times: 12, 15 and 20ns
Fast OE# access times: 6, 7 and 8ns
Single +5V +10% power supply
Fully static -- no clock or timing strobes necessary
All inputs and outputs are TTL-compatible
Three state outputs
Center power and ground pins for greater noise immunity
JEDEC standard for functionality and revolutionary pinout
Easy memory expansion with CE# and OE# options
Automatic CE# power down
High-performance, low-power consumption, CMOS
double-poly, double-metal process
OPTIONS
Timing
12ns access
15ns access
20ns access
MARKING
-12
-15
-20
Packages
36-pin SOJ (400 mil)
J
Power consumption
Standard
Low
None
L
Temperature
Commercial
Industrial
None
I
(
0°C
to
70°C)
(
-40°C
to
85°C)
GENERAL DESCRIPTION
The GVT72512A8 is organized as a 524,288 x 8 SRAM
using a four-transistor memory cell with a high performance,
silicon gate, low-power CMOS process. Galvantech SRAMs
are fabricated using double-layer polysilicon, double-layer
metal technology.
This device offers center power and ground pins for
improved performance and noise immunity. Static design
eliminates the need for external clocks or timing strobes. For
increased system flexibility and eliminating bus contention
problems, this device offers chip enable (CE#) and output
enable (OE#) with this organization.
Writing to these devices is accomplished when write
enable (WE#) and chip enable (CE#) inputs are both LOW.
Reading is accomplished when (CE#) and (OE#) go LOW
with (WE#) remaining HIGH. The device offers a low power
standby mode when chip is not selected. This allows system
designers to meet low standby power requirements.
1
2
3
4
5
6
7
8
9
10
32
31
30
29
28
27
26
25
24
23
22
21
20
11
12
13
14
15
16
19
A17
A16
A15
OE#
DQ8
DQ7
VSS
VCC
DQ6
DQ5
A14
A13
A12
A11
A10
NC
A2
A3
A4
DQ3
DQ4
WE#
A5
A6
A7
A8
A9
CE#
DQ1
DQ2
VCC
VSS
A18
A1
PIN ASSIGNMENT
36-Pin SOJ
NC
A0
17
18
35
34
33
36
相關PDF資料 |
PDF描述 |
|---|---|
| GVT72512A8J-15LI | x8 SRAM |
| GVT72512A8J-20 | x8 SRAM |
| GVT72512A8J-20I | x8 SRAM |
| GVT72512A8J-20L | x8 SRAM |
| GVT72512A8J-20LI | x8 SRAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| GVT72512A8J-15LI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| GVT72512A8J-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| GVT72512A8J-20I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| GVT72512A8J-20L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| GVT72512A8J-20LI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
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