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參數(shù)資料
| 型號(hào)： | HC125 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | QUAD BUS BUFFERS 3-STATE |
| 中文描述： | 四總線緩沖器的三態(tài) |
| 文件頁(yè)數(shù)： | 1/8頁(yè) |
| 文件大?。?/td> | 61K |
| 代理商： | HC125 |
74VHC125
QUAD BUS BUFFERS (3-STATE)
PRELIMINARY DATA
June 1999
PIN CONNECTION AND IEC LOGIC SYMBOLS
I
HIGHSPEED:t
PD
=3.8ns(TYP.)atV
CC
= 5V
I
LOWPOWERDISSIPATION:
I
CC
=4
μ
A(MAX.) at T
A
=25
o
C
I
HIGHNOISEIMMUNITY:
V
NIH
= V
NIL
=28%V
CC
(MIN.)
I
POWERDOWN PROTECTIONON INPUTS
I
SYMMETRICALOUTPUTIMPEDANCE:
|I
OH
| = I
OL
= 8 mA(MIN)
I
BALANCEDPROPAGATIONDELAYS:
t
PLH
t
PHL
I
OPERATINGVOLTAGERANGE:
V
CC
(OPR)= 2Vto 5.5V
I
PINANDFUNCTION COMPATIBLEWITH
74SERIES125
I
IMPROVEDLATCH-UP IMMUNITY
I
LOWNOISE:V
OLP
= 0.8V(Max.)
DESCRIPTION
The 74VHC125 is an advanced high-speed
CMOS QUAD BUS BUFFERS fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology.
This device requires the 3-STATE control input G
to be set high to place the output into the high
impedancestate.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface5V to 3V.
All
inputs
and
outputs are
protection circuits against static discharge, giving
them 2kV ESD immunity and transient excess
voltage.
equipped with
ORDER CODES :
74VHC125M
74VHC125T
M
(Micro Package)
T
(TSSOPPackage)
1/8
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