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參數資料
| 型號： | HC165 |
| 廠商： | System Logic Semiconductor Co., Ltd. |
| 英文描述： | 8-Bit Serial or Parallel-Input/ Serial-Output Shift Register |
| 中文描述： | 8位串行或并行輸入/串行輸出移位寄存器 |
| 文件頁數： | 1/7頁 |
| 文件大小： | 67K |
| 代理商： | HC165 |
SL74HC165
S ystem Logic
Semiconductor
SLS
8-Bit Serial or Parallel-Input/
Serial-Output Shift Register
High-Performance Silicon-Gate CMOS
The SL74HC165 is identical in pinout to the LS/ALS165. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
This device is an 8-bit shift register with complementary outputs
from the last stage. Data may be loaded into the register either in
parallel or in serial form. When the Serial Shift/ Parallel Load input is
low, the data is loaded asynchronously in parallel. When the Serial
Shift/Parallel Load input is high, the data is loaded serially on the rising
edge of either Clock or Clock Inhibit (see the Function Table).
The 2-input NOR clock may be used either by combining two
independent clock sources or by designating one of the clock inputs to
act as a clock inhibit.
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0
μ
A
High Noise Immunity Characteristic of CMOS Devices
LOGIC DIAGRAM
ORDERING INFORMATION
SL74HC165N Plastic
SL74HC165D SOIC
T
A
= -55
°
to 125
°
C for all packages
PIN 16=V
CC
PIN 8 = GND
FUNCTION TABLE
Inputs
Internal Stages
Output
Operation
Serial Shift/
Parallel Load
Clock
Clock
Inhibit
S
A
A-H
Q
A
Q
B
-Q
G
Q
H
L
H
X
X
a...h
a
b-g
h
Asynchronous Parallel Load
H
L
L
X
L
Q
An
-Q
Fn
Q
Gn
Serial Shift via Clock
H
L
H
X
H
Q
An
-Q
Fn
Q
Gn
H
H
L
L
L
H
X
X
L
H
Q
An
-Q
Fn
Q
An
-Q
Fn
Q
Gn
Q
Gn
Serial Shift via Clock
Inhibit
H
X
H
X
X
no change
Inhibited Clock
H
H
X
X
X
H
L
L
X
X
no change
No Clock
X = Don’t Care
Q
An
-Q
Fn
= Data shifted from the preceding stage
PIN ASSIGNMENT
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