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參數資料
型號: HC2510
廠商: Hynix Semiconductor Inc.
英文描述: Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications
中文描述: 鎖相環時鐘的同步DRAM應用分布
文件頁數: 3/6頁
文件大小: 81K
代理商: HC2510
HC2510C
3
Table 1. Pin Description
Pin Name
Pin No.
Type
Functional Description
CLK
24
I
Clock Input. CLK provides the reference signal to the internal
PLL.
Feedback Input. FBIN provides the feedback signal to the
internal PLL.
Output Bank Enable. When G is high, all outputs 1Y(0:9) are
enabled.
When G is low, Outputs 1Y(0:9) are disable to a logic-low
state.
Feedback Output. FBOUT completes the feedback loop of the
PLL by being wired to FBIN.
Clock Outputs. These outputs provide low-skew copies of
CLKIN. Each output has an embedded series-damping
resistor.
Analog Power Supply. AV
cc
provides the power reference for
the analog circuitry. AV
cc
can be also used to bypass the PLL
for the test purpose. When AV
cc
is strapped to ground, PLL is
bypassed and CLK is buffered directly to the device outputs.
Analog Ground. AGND provides the ground reference for the
analog circuitry.
Power Power Supply
Groun
d
FBIN
13
I
G
11
I
FBOUT
12
O
1Y(0:9)
3,4,5,8,9
15,16,17,20,2
1
O
AV
cc
23
Power
AGND
1
Groun
d
V
cc
2,10,14,22
GND
6,7,18,19
Ground
Table 2. Absolute Maximum Ratings Over Operating Free-air
Temperature Range
Symbols
Parameter
Value
Unit
Conditions
V
cc
V
I
Supply Voltage Range
Input Voltage Range
Voltage Range applied to any
input in the high or low state
Input Clamp Current
-0.5 to 4.6
-0.5 to 6.5
V
V
V
o
-0.5 to Vcc+0.5
V
I
IK
±
50
±
50
±
50
0.7
mA
V
I
<0 or V
I
>V
cc
I
OK
Output Clamp Current
mA
V
o
<0 or V
o
>V
cc
I
o
Continuous Output Current
Maximum Power Dissipaiton
Storage Temperature Range
mA
W
°
C
V
o
=0 to V
cc
P
MAX
T
stg
- 65 to 150
相關PDF資料
PDF描述
HC2510C Voltage Regulator IC; Output Voltage:5.6V; Package/Case:16-DIP; Supply Voltage Max:35V; Output Current Max:500mA; Output Current Min:-500mA; Voltage Regulator Type:PWM; Mounting Type:Through Hole; Supply Voltage Min:8V
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相關代理商/技術參數
參數描述
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HC2510C 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications
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