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參數(shù)資料
| 型號(hào)： | HC257 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | T-NPN- SI-AF PO |
| 中文描述： | 四2通道多路復(fù)用三態(tài) |
| 文件頁數(shù)： | 1/14頁 |
| 文件大小： | 315K |
| 代理商： | HC257 |
1/14
November 2004
I
HIGH SPEED: t
PD
= 3.7ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 4
μ
A (MAX.) at T
A
=25°C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28% V
CC
(MIN.)
POWER DOWN PROTECTION ON INPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 257
IMPROVED LATCH-UP IMMUNITY
LOW NOISE: V
OLP
= 0.8V (MAX.)
I
I
I
I
I
I
I
I
I
DESCRIPTION
The 74VHC257 is an advanced high-speed
CMOS
QUAD 2-CHANNEL
(3-STATE) fabricated with sub-micron silicon gate
and double-layer metal wiring C
2
MOS technology.
It is composed of four independent 2-channel
multiplexers with common SELECT and ENABLE
(OE) INPUT. The VHC257 is a non-inverting
multiplexer. When the ENABLE INPUT is held
MULTIPLEXER
"High", all outputs become in high impedance
state. If SELECT INPUT is held "Low", "A" data is
selected, when SELECT INPUT is "High", "B" data
is chosen.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74VHC257
QUAD 2 CHANNEL MULTIPLEXER (3-STATE)
Figure 1: Pin Connection And IEC Logic Symbols
Table 1: Order Codes
PACKAGE
T & R
SOP
TSSOP
74VHC257MTR
74VHC257TTR
TSSOP
SOP
Rev. 4
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