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參數(shù)資料
| 型號： | HC4046 |
| 廠商： | System Logic Semiconductor Co., Ltd. |
| 英文描述： | Phase-Locked Loop |
| 中文描述： | 鎖相環(huán) |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 134K |
| 代理商： | HC4046 |
SL74HC4046
S ystem Logic
Semiconductor
SLS
[Demodulator Section]
DC ELECTRICAL CHARACTERISTICS
V
CC
Guaranteed Limit
Symbol
Parameter
Test Conditions
V
25
°
C to
-55
°
C
≤
85
°
C
≤
125
°
C
Unit
Min
Max
Min
Max
Min
Max
RS
Resistor Range
At RS > 300 k
the Leakage
Current can
Influence
VDEM
OUT
3.0
4.5
6.0
50
50
50
300
300
300
k
V
OFF
Offset Voltage VCO
IN
to VDEM
OUT
V
I
= VVCO
IN
= 1/2
V
CC
; Values taken
over RS Range
3.0
4.5
6.0
See Figure 10
mV
RD
Dynamic Output
Resistance at DEM
OUT
VDEM
OUT
=
1/2 V
CC
3.0
4.5
6.0
Typical 25
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
Figure 4. Test Circuit
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