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參數資料
| 型號： | HC74 |
| 廠商： | System Logic Semiconductor Co., Ltd. |
| 英文描述： | T-NPN-SI PWR AMP |
| 中文描述： | 雙D觸發器的設置和復位拖鞋（高性能硅柵CMOS） |
| 文件頁數： | 4/5頁 |
| 文件大小： | 51K |
| 代理商： | HC74 |
SL74HC74
S ystem Logic
Semiconductor
SLS
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Guaranteed Limit
Symbol
Parameter
V
25
°
C
to
-55
°
C
≤
85
°
C
≤
125
°
C
Unit
f
max
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
2.0
4.5
6.0
6.0
30
35
4.8
24
28
4.0
20
24
MHz
t
PLH
, t
PHL
Maximum Propagation Delay, Clock to Q or Q
(Figures 1 and 4)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
t
PLH
, t
PHL
Maximum Propagation Delay, Set or Reset to Q
or Q (Figures 2 and 4)
2.0
4.5
6.0
105
21
18
130
26
22
160
32
27
ns
t
TLH
, t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
C
IN
Maximum Input Capacitance
-
10
10
10
pF
Power Dissipation Capacitance (Per Flip-Flop)
Typical @25
°
C,V
CC
=5.0 V
C
PD
Used to determine the no-load dynamic power
consumption:
P
D
=C
PD
V
CC
2
f+I
CC
V
CC
39
pF
TIMING REQUIREMENTS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Guaranteed Limit
Symbol
Parameter
V
25
°
C to-55
°
C
≤
85
°
C
≤
125
°
C
Unit
t
su
Minimum Setup Time, Data to Clock
(Figure 3)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
t
h
Minimum Hold Time, Clock to Data
(Figure 3)
2.0
4.5
6.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
ns
t
rec
Minimum Recovery Time, Set or Reset
Inactive to Clock (Figure 2)
2.0
4.5
6.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
ns
t
w
Minimum Pulse Width, Clock (Figure
1)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
t
w
Minimum Pulse Width, Set or Reset
(Figure 2)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
t
r
, t
f
Maximum Input Rise and Fall Times
(Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns
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