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參數資料
| 型號： | HCA10014 |
| 廠商： | Intersil Corporation |
| 英文描述： | Darlington Bipolar Transistor; Package/Case:TO-3; Current Rating:50A; Voltage Rating:120V |
| 中文描述： | 15MHz的，BiMOS運算放大器MOSFET的輸入/ CMOS輸出 |
| 文件頁數： | 8/17頁 |
| 文件大小： | 521K |
| 代理商： | HCA10014 |
8
Power Supply Considerations
Because the HCA10014 is very useful in single supply
applications, it is pertinent to review some considerations
relating to power supply current consumption under both
single and dual supply service. Figures 12A and 12B show
connections for both dual and single supply operation.
Dual Supply Operation -
When the output voltage at
Terminal 6 is 0V, the currents supplied by the two power
supplies are equal. When the gate terminals of Q
8
and Q
12
are driven increasingly positive with respect to ground,
current flow through Q
12
(from the negative supply) to the
load is increased and current flow through Q
8
(from the
positive supply) decreases correspondingly. When the gate
terminals of Q
8
and Q
12
are driven increasingly negative
with respect to ground, current flow through Q
8
is increased
and current flow through Q
12
is decreased accordingly.
Single Supply Operation -
Initially, let it be assumed that
the value of R
L
is very high (or disconnected), and that the
input terminal bias (Terminals 2 and 3) is such that the
output terminal (No. 6) voltage is at V+/2, i.e., the voltage
drops across Q
8
and Q
12
are of equal magnitude. Figure 4
shows typical quiescent supply current vs supply voltage for
the HCA10014 operated under these conditions. Since the
output stage is operating as a Class A amplifier, the supply
current will remain constant under dynamic operating
conditions as long as the transistors are operated in the
linear portion of their voltage transfer characteristics (see
Figure 8). If either Q
8
or Q
12
are swung out of their linear
regions toward cutoff (a nonlinear region), there will be a
corresponding reduction in supply current. In the extreme
case, e.g., with Terminal 8 swung down to ground potential
(or tied to ground), NMOS transistor Q
12
is completely cut
off and the supply current to series connected transistors
Q
8
, Q
12
goes essentially to zero. The two preceding stages,
however, continue to draw modest supply current (see the
lower curve in Figure 4) even though the output stage is
strobed off. Figure 12A shows a dual supply arrangement for
the output stage that can also be strobed off, assuming
R
L
=
∞
by pulling the potential of Terminal 8 down to that of
Terminal 4.
Let it now be assumed that a load resistance of nominal
value (e.g., 2k
) is connected between Terminal 6 and
ground in the circuit of Figure 12B. Let it be assumed again
that the input terminal bias (Terminals 2 and 3) is such that
the output terminal (No. 6) voltage is at V+/2. Since PMOS
transistor Q
8
must now supply quiescent current to both R
L
and transistor Q
12
, it should be apparent that under these
conditions the supply current must increase as an inverse
function of the R
L
magnitude. Figure 5 shows the voltage
drop across PMOS transistor Q
8
as a function of load
current at several supply voltages. Figure 8 shows the
voltage transfer characteristics of the output stage for
several values of load resistance.
Wideband Noise
From the standpoint of low noise performance
considerations, the use of the HCA10014 is most
advantageous in applications where the source resistance
of the input signal is on the order of 1M
or more. In this
case, the total input referred noise voltage is typically only
23
μ
V when the test circuit amplifier of Figure 13 is
operated at a total supply voltage of 15V. This value of total
input referred noise remains essentially constant, even
though the value of source resistance is raised by an order
of magnitude. This characteristic is due to the fact that
reactance of the input capacitance becomes a significant
factor in shunting the source resistance. It should be noted,
however, that for values of source resistance very much
greater than 1M
, the total noise voltage generated can be
dominated by the thermal noise contributions of both the
feedback and source resistors.
FIGURE 12A. DUAL POWER SUPPLY OPERATION
FIGURE 12B. SINGLE POWER SUPPLY OPERATION
FIGURE 12. OUTPUT STAGE IN DUAL AND SINGLE POWER SUPPLY OPERATION
3
2
8
4
7
6
R
L
Q
8
Q
12
+
-
V+
V-
3
2
8
4
7
6
R
L
Q
8
Q
12
+
-
V+
HCA10014
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