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參數資料
| 型號： | HCC4029BF |
| 廠商： | 意法半導體 |
| 英文描述： | Dual Line Receiver 14-SOIC 0 to 70 |
| 中文描述： | 二進制或BCD十年預置加/減計數器 |
| 文件頁數： | 1/13頁 |
| 文件大小： | 295K |
| 代理商： | HCC4029BF |
HCC4029B
HCF4029B
September 1988
BINARY OR BCD DECADE
PRESETTABLE UP/DOWN COUNTER
EY
(Plastic Package)
DESCRIPTION
ORDER CODES :
HCC4029BF
HCF4029BEY
HCF4029BM1
HCF4029BC1
F
(CeramicPackage)
M1
(MicroPackage)
C1
(Chip Carrier)
PIN CONNECTIONS
NC = No Internal Connection
The
HCC4029B
(extended temperature range) and
HCF4029B
(intermediate temperature range) are
monolithic integrated circuit, available in 16-lead
dual in-line plastic or ceramic package and plastic
micro package. The
HCC/HCF4029B
consistsof a
four-stage binary or BCD-decade up/down counter
withprovisions forlook-ahead carry in bothcounting
modes. The inputs consist of a single CLOCK,
CARRY-IN(CLOCK ENABLE), BINARY/DECADE,
UP/DOWN, PRESET ENABLE, and four individual
JAM signals. Q1, Q2, Q3, Q4 and a CARRY OUT
signalareprovided asoutputs. Ahigh PRESET EN-
ABLEsignal allows information ontheJAM INPUTS
to preset the counter to any state asynchronously
with the clock. A low on each JAM line, when the
PRESET-ENABLE signal ishigh, resets the counter
to itszerocount. Thecounter isadvanced onecount
at the positive transition of the clock when the
CARRY-INand PRESET ENABLE signals, arelow.
Advancement is inhibited when the CARRY-IN or
PRESET ENABLE signals are high. The CARRY-
OUT signal is normally high and goes lowwhen the
.
MEDIUM SPEED OPERATION - 8MHz (typ.) @
C
L
= 50pF ANDV
DD
-V
SS
= 10V
.
MULTI-PACKAGE PARALLEL CLOCKINGFOR
SYNCHRONOUSHIGH SPEED OUTPUT RES-
PONSE OR RIPPLE CLOCKING FOR SLOW
CLOCKINPUT RISE ANDFALL TIMES
.
”PRESET ENABLE” AND INDIVIDUAL ”JAM”
INPUTSPROVIDED
.
BINARY OR DECADE UP/DOWN COUNTING
.
BCD OUTPUTSIN DECADEMODE
.
STANDARDIZED
CHARACTERISTICS
.
5V, 10V, AND 15V PARAMETRIC RATINGS
.
INPUT CURRENTOF100nA AT18V AND 25
°
C
FOR HCC DEVICE
.
QUIESCENT CURRENT SPECIFIED TO 20V
FOR HCC DEVICE
.
100% TESTEDFOR QUIESCENTCURRENT
.
MEETSALLREQUIREMENTSOFJEDECTEN-
TATIVE STANDARD N
o
. 13A, ”STANDARD
SPECIFICATIONS FOR DESCRIPTION OF ”B”
SERIESCMOS DEVICES”
SYMMETRICAL
OUTPUT
1/13
相關PDF資料 |
PDF描述 |
|---|---|
| HCF4029BEY | Quadruple Differential Line Receiver 16-PDIP 0 to 70 |
| HCF4029BM1 | BINARY OR BCD DECADE PRESETTABLE UP/DOWN COUNTER |
| HCC4030B | QUAD EXCLUSIVE-OR GATE |
| HCC4030BF | Dual Line Receiver 14-SOIC 0 to 70 |
| HCC4031B | 64-STAGE STATIC SHIFT REGISTER |
相關代理商/技術參數 |
參數描述 |
|---|---|
| HCC4029BK | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| HCC4030B | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:RadHardened high voltage complementary MOS logic series |
| HCC4030BD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| HCC4030BF | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:QUAD EXCLUSIVE-OR GATE |
| HCC4030BK | 制造商:STMicroelectronics 功能描述:SPACE LEVEL: - Bulk |
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