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參數(shù)資料
| 型號(hào)： | HCF4724BEY |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | 通用總線功能 |
| 英文描述： | 8 BIT ADDRESSABLE LATCH |
| 中文描述： | 8位可尋址鎖存 |
| 文件頁(yè)數(shù)： | 1/14頁(yè) |
| 文件大小： | 302K |
| 代理商： | HCF4724BEY |
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HCC4724B
HCF4724B
September 1988
8 BIT ADDRESSABLE LATCH
EY
(Plastic Package)
DESCRIPTION
ORDER CODES :
HCC4724BF
HCF4724BEY
HCF4724BM1
HCF4724BC1
F
(CeramicPackage)
M1
(MicroPackage)
C1
(Chip Carrier)
PIN CONNECTIONS
The
HCC/HCF4724B
8-bit addressable latch is a
serial-input, parallel-output storageregister thatcan
perform a variety of functions.
Dataare inputted to a particular bit inthe latch when
that bitis addressed (by meansofinputs A0,A1,A2)
and when WRITE DISABLE is at low level. When
WRITE DISABLE is high, data entry is inhibited
however, all 8 outputs can be continuously readin-
dependent of WRITEDISABLE andaddress inputs.
A masterRESET input is available, which resets all
bits to a logic ” 0 ” level when RESET and WRITE
DISABLE are at a high level. When RESET is at a
highlevel, and WRITEDISABLE isatalowlevel,the
latch acts as a 1-of-8 demultiplexer ; the bit that is
addressed has an active output which follows the
data input, while all unaddressed bits are held to a
logic ” 0 ” level.
.
SERIAL DATA INPUT - ACTIVE PARALLEL
OUTPUT
.
STORAGEREGISTER CAPABILITY - MASTER
CLEAR
.
CAN FUNCTIONAS DEMULTIPLEXER
.
STANDARDIZED, SYMMETRICAL OUTPUT
CHARACTER
.
100% TESTED FOR QUIESCENT CURRENT
AT 20V
.
MAXIMUM INPUT CURRENT OF 1
μ
A AT 18V
(fullpackage-temperature range), 100nA AT18V
AND 25
o
C
.
NOISE
range)= 1VATV
DD
=5V, 2VATV
DD
=10V,2.5V
AT V
DD
= 15V
.
5V, 10V, AND 15V PARAMETRIC RATINGS
.
MEETSALLREQUIREMENTSOFJEDECTEN-
TATIVE STANDARD N. 13A, ” STANDARD
SPECIFICATIONS FOR DESCRIPTION OF ’ B
’ SERIESCMOS DEVICES”
.
MULTI-LINEDECODERS
.
A/D CONVERTERS
MARGIN
(full
package-temperature
APPLICATION
1/14
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