- 您現在的位置：買賣IC網 > PDF目錄371784 > HCS74DTR (INTERSIL CORP) Low-Voltage, Dual Hot-Swap Controllers with Independent On/Off Control PDF資料下載
參數資料
| 型號： | HCS74DTR |
| 廠商： | INTERSIL CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Low-Voltage, Dual Hot-Swap Controllers with Independent On/Off Control |
| 中文描述： | HC/UH SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14 |
| 封裝： | SIDE BRAZED, CERAMIC, DIP-14 |
| 文件頁數： | 1/9頁 |
| 文件大小： | 175K |
| 代理商： | HCS74DTR |
83
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
Ordering Information
PART NUMBER
TEMPERATURE RANGE
SCREENING LEVEL
PACKAGE
HCS74DMSR
-55
o
C to +125
o
C
Intersil Class S Equivalent
14 Lead SBDIP
HCS74KMSR
-55
o
C to +125
o
C
Intersil Class S Equivalent
14 Lead Ceramic Flatpack
HCS74D/Sample
+25
o
C
Sample
14 Lead SBDIP
HCS74K/Sample
+25
o
C
Sample
14 Lead Ceramic Flatpack
HCS74HMSR
+25
o
C
Die
Die
HCS74MS
Radiation Hardened Dual-D
Flip-Flop with Set and Reset
Pinouts
14 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T14, LEAD FINISH C
TOP VIEW
14 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP3-F14, LEAD FINISH C
TOP VIEW
R1N
D1
CP1
S1N
Q1
Q1N
GND
VCC
R2N
D2
CP2
S2N
Q2
Q2N
1
2
3
4
5
6
7
14
13
12
11
10
9
8
14
13
12
11
10
9
8
2
3
4
5
6
7
1
R1
D1
CP1
S1
Q1
Q1
GND
VCC
R2
D2
CP2
S2
Q2
Q2
Features
3 Micron Radiation Hardened SOS CMOS
Total Dose 200K RAD (Si)
SEP Effective LET No Upsets: >100 MEV-cm
2
/mg
Single Event Upset (SEU) Immunity < 2 x 10
-9
Errors/
Bit-Day (Typ)
Dose Rate Survivability: >1 x 10
12
RAD (Si)/s
Dose Rate Upset >10
10
RAD (Si)/s 20ns Pulse
Latch-Up Free Under Any Conditions
Military Temperature Range: -55
o
C to +125
o
C
Significant Power Reduction Compared to LSTTL ICs
DC Operating Voltage Range: 4.5V to 5.5V
Input Logic Levels
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
Input Current Levels Ii
≤
5
μ
A at VOL, VOH
Description
The Intersil HCS74MS is a Radiation Hardened positive
edge triggered flip-flop with set and reset.
The HCS74MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCS74MS is supplied in a 14 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
September 1995
Spec Number
518772
File Number
2142.2
相關PDF資料 |
PDF描述 |
|---|---|
| HCS74K | Radiation Hardened Dual-D Flip-Flop with Set and Reset |
| HCS74KMSR | Radiation Hardened Dual-D Flip-Flop with Set and Reset |
| HCS74KTR | Radiation Hardened Dual-D Flip-Flop with Set and Reset |
| HCS86HMSR | Radiation Hardened Quad 2-Input Exclusive OR Gate |
| HCS86MS | Radiation Hardened Quad 2-Input Exclusive OR Gate(抗輻射四2輸入異或門) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| HCS74HMSR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Dual-D Flip-Flop with Set and Reset |
| HCS74K | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Dual-D Flip-Flop with Set and Reset |
| HCS74KMSR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Dual-D Flip-Flop with Set and Reset |
| HCS74KTR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Dual-D Flip-Flop with Set and Reset |
| HCS74MS | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Dual-D Flip-Flop with Set and Reset |
發布緊急采購，3分鐘左右您將得到回復。