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參數資料
| 型號： | HCTS112K |
| 廠商： | Intersil Corporation |
| 英文描述： | Radiation Hardened Dual JK Flip-Flop |
| 中文描述： | 輻射加固雙JK觸發器 |
| 文件頁數： | 1/10頁 |
| 文件大?。?/td> | 180K |
| 代理商： | HCTS112K |
490
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
Ordering Information
PART NUMBER
TEMPERATURE RANGE
SCREENING LEVEL
PACKAGE
HCTS112DMSR
-55
o
C to +125
o
C
Intersil Class S Equivalent
16 Lead SBDIP
HCTS112KMSR
-55
o
C to +125
o
C
Intersil Class S Equivalent
16 Lead Ceramic Flatpack
HCTS112D/Sample
+25
o
C
Sample
16 Lead SBDIP
HCTS112K/Sample
+25
o
C
Sample
16 Lead Ceramic Flatpack
HCTS112HMSR
+25
o
C
Die
Die
HCTS112MS
Radiation Hardened
Dual JK Flip-Flop
Pinouts
16 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T16
TOP VIEW
16 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP4-F16
TOP VIEW
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
CP1
K1
J1
S1
Q1
Q1
GND
Q2
VCC
R2
CP2
K2
J2
S2
Q2
R1
CP1
K1
J1
S1
Q1
Q1
Q2
GND
2
3
4
5
6
7
8
1
16
15
14
13
12
11
10
9
VCC
R1
R2
CP2
K2
J2
S2
Q2
Features
3 Micron Radiation Hardened SOS CMOS
Total Dose 200K RAD (Si)
SEP Effective LET No Upsets: >100 MEV-cm
2
/mg
Single Event Upset (SEU) Immunity < 2 x 10
-9
Errors/
Bit-Day (Typ)
Dose Rate Survivability: >1 x 10
12
RAD (Si)/s
Dose Rate Upset >10
10
RAD (Si)/s 20ns Pulse
Cosmic Ray Upset Rate 2 x 10
-9
Errors/Bit Day (Typ)
Latch-Up Free Under Any Conditions
Military Temperature Range: -55
o
C to +125
o
C
Significant Power Reduction Compared to LSTTL ICs
DC Operating Voltage Range: 4.5V to 5.5V
LSTTL Input Compatibility
- VIL = 0.8V Max
- VIH = VCC/2 Min
Input Current Levels Ii
≤
5
μ
A at VOL, VOH
Description
The Intersil HCTS112MS is a Radiation Hardened dual JK
flip-flop with set and reset. The flip-flop changes states with
the negative transition of the clock (CP1N or CP2N).
The HCTS112MS utilizes advanced CMOS/SOS technology
to achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCTS112MS is supplied in a 16 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
September 1995
Spec Number
518603
File Number
2467.2
D
相關PDF資料 |
PDF描述 |
|---|---|
| HCTS112KMSR | Radiation Hardened Dual JK Flip-Flop |
| HCTS112MS | Radiation Hardened Dual JK Flip-Flop |
| HCTS112HMSR | Radiation Hardened Dual JK Flip-Flop |
| HCTS11MS | Quadruple 2-Input Positive-NAND Gate 20-LCCC -55 to 125 |
| HCTS160KMSR | Radiation Hardened Synchronous Counter |
相關代理商/技術參數 |
參數描述 |
|---|---|
| HCTS112KMSR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Dual JK Flip-Flop |
| HCTS112MS | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Dual JK Flip-Flop |
| HCTS11MS | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Triple 3-Input AND Gate |
| HCTS132D | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Quad 2-Input NAND Schmitt Trigger |
| HCTS132DMSR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Quad 2-Input NAND Schmitt Trigger |
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