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參數資料
| 型號： | HCTS147MS |
| 廠商： | Intersil Corporation |
| 英文描述： | Quadruple 2-Input Positive-AND Gates 14-CDIP -55 to 125 |
| 中文描述： | 輻射加固10到4線優先編碼器 |
| 文件頁數： | 1/10頁 |
| 文件大小： | 180K |
| 代理商： | HCTS147MS |
530
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
Ordering Information
PART NUMBER
TEMPERATURE RANGE
SCREENING LEVEL
PACKAGE
HCTS147DMSR
-55
o
C to +125
o
C
Intersil Class S Equivalent
16 Lead SBDIP
HCTS147KMSR
-55
o
C to +125
o
C
Intersil Class S Equivalent
16 Lead Ceramic Flatpack
HCTS147D/Sample
+25
o
C
Sample
16 Lead SBDIP
HCTS147K/Sample
+25
o
C
Sample
16 Lead Ceramic Flatpack
HCTS147HMSR
+25
o
C
Die
Die
HCTS147MS
Radiation Hardened
10-to-4 Line Priority Encoder
Pinouts
16 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T16
TOP VIEW
16 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP4-F16
TOP VIEW
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
I4
I5
I6
I7
I8
Y2
GND
Y1
VCC
Y3
I3
I2
I1
I9
Y0
NC
2
3
4
5
6
7
8
1
16
15
14
13
12
11
10
9
I4
I5
I6
I7
I8
Y2
GND
Y1
VCC
Y3
I3
I2
I1
I9
Y0
NC
Features
3 Micron Radiation Hardened SOS CMOS
Total Dose 200K RAD (Si)
SEP Effective LET No Upsets: >100 MEV-cm
2
/mg
Single Event Upset (SEU) Immunity < 2 x 10
-9
Errors/
Bit-Day (Typ)
Dose Rate Survivability: >1 x 10
12
RAD (Si)/s
Dose Rate Upset >10
10
RAD (Si)/s 20ns Pulse
Latch-Up Free Under Any Conditions
Fanout (Over Temperature Range)
- Bus Driver Outputs - 15 LSTTL Loads
Military Temperature Range: -55
o
C to +125
o
C
Significant Power Reduction Compared to LSTTL ICs
DC Operating Voltage Range: 4.5V to 5.5V
LSTTL Input Compatibility
- VIL = 0.8V Max
- VIH = VCC/2 Min
Input Current Levels Ii
≤
5
μ
A at VOL, VOH
Description
The Intersil HCTS147MS is a Radiation Hardened 10-to-4
line Priority Encoder, pin compatible with low power Schottky
TTL(LSTTL).
The HCTS147MS utilizes advanced CMOS/SOS technology
to achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family
with TTL input compatibility.
The HCTS147MS is supplied in a 16 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
September 1995
Spec Number
518608
File Number
3063.1
D
相關PDF資料 |
PDF描述 |
|---|---|
| HCTS147HMSR | Radiation Hardened 10-to-4 Line Priority Encoder |
| HCTS14HMSR | Test RoHS Compliant: NA |
| HCTS14KMSR | CAPACITOR .0033UF 200V M SERIES |
| HCTS14D | Quadruple 2-Input Positive-AND Gates 14-CFP -55 to 125 |
| HCTS14DMSR | Radiation Hardened HEX Inverting Schmitt Trigger |
相關代理商/技術參數 |
參數描述 |
|---|---|
| HCTS14D | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened HEX Inverting Schmitt Trigger |
| HCTS14DMSR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened HEX Inverting Schmitt Trigger |
| HCTS14HMSR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened HEX Inverting Schmitt Trigger |
| HCTS14K | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened HEX Inverting Schmitt Trigger |
| HCTS14K/SAMPLE | 制造商:Intersil Corporation 功能描述:HEX INVERTING SCHMITT TRIGGER |
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