
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
Ordering Information
PART NUMBER
TEMPERATURE RANGE
SCREENING LEVEL
PACKAGE
HCTS190DMSR
-55
o
C to +125
o
C
Intersil Class S Equivalent
16 Lead SBDIP
HCTS190KMSR
-55
o
C to +125
o
C
Intersil Class S Equivalent
16 Lead Ceramic Flatpack
HCTS190D/Sample
+25
o
C
Sample
16 Lead SBDIP
HCTS190K/Sample
+25
o
C
Sample
16 Lead Ceramic Flatpack
HCTS190HMSR
+25
o
C
Die
Die
HCTS190MS
Radiation Hardened
Synchronous 4-Bit Up/Down Counter
Description
The Intersil HCTS190MS is an asynchronously presettable
BCD Decade synchronous counter. Presetting the counter to
the number on the preset data inputs (P0 - P3) is accom-
plished by a low on the parallel load input (PL). Counting
occurs when (PL) is high, Count Enable (CE) is low and the
Up/Down (U/D) input is either low for up-counting or high for
down-counting. The counter is incremented or decremented
synchronously with the low-to-high transition of the clock.
When an overflow or underflow of the counter occurs, the
Terminal Count output (TC), which is low during counting,
goes high and remains high for one clock cycle. This output
can be used for look-ahead carry in high speed cascading.
The TC output also initiates the Ripple Clock output (RC)
which, normally high, goes low and remains low for the low-
level portion of the clock pulse. These counter can be cas-
caded using the Ripple Carry output.
If the decade counter is preset to an illegal state or assumes
an illegal state when power is applied, it will return to the
normal sequence in one or two counts
The HCTS190MS utilizes advanced CMOS/SOS technology
to achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCTS190MS is supplied in a 16 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Features
3 Micron Radiation Hardened CMOS SOS
Total Dose 200K RAD (Si)
SEP Effective LET No Upsets: >100 MEV-cm
2
/mg
Single Event Upset (SEU) Immunity < 2 x 10
-9
Errors/
Bit-Day (Typ)
Dose Rate Survivability: >1 x 10
12
RAD (Si)/s
Dose Rate Upset >10
10
RAD (Si)/s 20ns Pulse
Latch-Up Free Under Any Conditions
Fanout (Over Temperature Range)
- Standard Outputs - 10 LSTTL Loads
Military Temperature Range: -55
o
C to +125
o
C
Significant Power Reduction Compared to LSTTL ICs
DC Operating Voltage Range: 4.5V to 5.5V
LSTTL Input Compatibility
- VIL = 0.8V Max
- VIH = VCC/2 Min
Input Current Levels Ii
≤
5
μ
A @ VOL, VOH
September 1995
Spec Number
518614
File Number
2474.2
Pinouts
16 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE
(SBDIP) MIL-STD-1835 CDIP2-T16, LEAD FINISH C
TOP VIEW
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
Q1
Q0
CE
U/D
Q2
GND
Q3
CP
RC
TC
PL
P2
P0
P1
VCC
P3
16 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
(FLATPACK) MIL-STD-1835 CDFP4-F16, LEAD FINISH C
TOP VIEW
2
3
4
5
6
7
8
1
16
15
14
13
12
11
10
9
Q1
Q0
CE
U/D
Q2
GND
Q3
P1
CP
RC
TC
PL
P2
P0
VCC
P3