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參數資料
| 型號： | HCTS273MS |
| 廠商： | Intersil Corporation |
| 英文描述： | Radiation Hardened Octal D Flip-Flop |
| 中文描述： | 輻射加固八路D觸發器 |
| 文件頁數： | 1/10頁 |
| 文件大小： | 281K |
| 代理商： | HCTS273MS |
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com
|
Copyright
Intersil Corporation 1999
Ordering Information
PART NUMBER
TEMPERATURE RANGE
SCREENING LEVEL
PACKAGE
HCTS273DMSR
-55
o
C to +125
o
C
Intersil Class S Equivalent
20 Lead SBDIP
HCTS273KMSR
-55
o
C to +125
o
C
Intersil Class S Equivalent
20 Lead Ceramic Flatpack
HCTS273D/Sample
+25
o
C
Sample
20 Lead SBDIP
HCTS273K/Sample
+25
o
C
Sample
20 Lead Ceramic Flatpack
HCTS273HMSR
+25
o
C
Die
Die
HCTS273MS
Radiation Hardened
Octal D Flip-Flop
Pinouts
20 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T20, LEAD FINISH C
TOP VIEW
20 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP4-F20, LEAD FINISH C
TOP VIEW
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
MR
Q0
D0
D1
Q1
Q2
D3
D2
Q3
GND
VCC
D7
D6
Q6
Q7
Q5
D5
D4
Q4
CP
2
3
4
5
6
7
8
9
10
1
20
19
18
17
16
15
14
13
12
11
MR
Q0
D0
D1
Q1
Q2
D2
D3
Q3
GND
VCC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
CP
Features
3 Micron Radiation Hardened CMOS SOS
Total Dose 200K RAD (Si)
SEP Effective LET No Upsets: >100 MEV-cm
2
/mg
Single Event Upset (SEU) Immunity < 2 x 10
-9
Errors/Bit-
Day (Typ)
Dose Rate Survivability: >1 x 10
12
RAD (Si)/s
Dose Rate Upset >10
10
RAD (Si)/s. 20ns Pulse
Latch-Up Free Under Any Conditions
Fanout (Over Temperature Range)
- Bus Driver Outputs - 15 LSTTL Loads
Military Temperature Range: -55
o
C to +125
o
C
Significant Power Reduction Compared to LSTTL ICs
DC Operating Voltage Range: 4.5V to 5.5V
LSTTL Input Compatibility
- VIL = 0.8V Max
- VIH = VCC/2 Min
Input Current Levels Ii
≤
5
μ
A at VOL, VOH
Description
The Intersil HCTS273MS is a Radiation Hardened octal D flip-
flop, positive edge triggered, with reset.
The HCTS273MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCTS273MS is supplied in a 20 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
September 1995
Spec Number
518642
File Number
2274.2
相關PDF資料 |
PDF描述 |
|---|---|
| HCTS273D | Radiation Hardened Octal D Flip-Flop |
| HCTS273DMSR | 512 x 36 x 2 Synchronous Bidirectional FIFO Memory 132-CFP -55 to 125 |
| HCTS273HMSR | Radiation Hardened Octal D Flip-Flop |
| HCTS27DMSR | Radiation Hardened Triple 3-Input NOR Gate |
| HCTS27D | Radiation Hardened Triple 3-Input NOR Gate |
相關代理商/技術參數 |
參數描述 |
|---|---|
| HCTS27D | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Triple 3-Input NOR Gate |
| HCTS27DMSR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Triple 3-Input NOR Gate |
| HCTS27HMSR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Triple 3-Input NOR Gate |
| HCTS27K | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Triple 3-Input NOR Gate |
| HCTS27KMSR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Triple 3-Input NOR Gate |
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