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參數資料
| 型號： | HCTS365MS |
| 廠商： | Intersil Corporation |
| 英文描述： | Radiation Hardened Hex Buffer/Line Driver Non-Inverting |
| 中文描述： | 輻射硬化六角緩沖器/線路驅動器非反相 |
| 文件頁數： | 1/10頁 |
| 文件大小： | 200K |
| 代理商： | HCTS365MS |
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
Ordering Information
PART NUMBER
TEMPERATURE RANGE
SCREENING LEVEL
PACKAGE
HCTS365DMSR
-55
o
C to +125
o
C
Intersil Class S Equivalent
16 Lead SBDIP
HCTS365KMSR
-55
o
C to +125
o
C
Intersil Class S Equivalent
16 Lead Ceramic Flatpack
HCTS365D/Sample
+25
o
C
Sample
16 Lead SBDIP
HCTS365K/Sample
+25
o
C
Sample
16 Lead Ceramic Flatpack
HCTS365HMSR
+25
o
C
Die
Die
HCTS365MS
Radiation Hardened
Hex Buffer/Line Driver Non-Inverting
Pinouts
16 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T16, LEAD FINISH C
TOP VIEW
16 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP4-F16, LEAD FINISH C
TOP VIEW
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
OE1
A1
Y1
A2
Y2
A3
GND
Y3
VCC
A6
Y6
A5
Y5
A4
Y4
OE2
OE1
A1
Y1
A2
Y2
A3
Y3
GND
2
3
4
5
6
7
8
1
16
15
14
13
12
11
10
9
VCC
OE2
A6
Y6
A5
Y5
A4
Y4
Features
3 Micron Radiation Hardened CMOS SOS
Total Dose 200K RAD (Si)
SEP Effective LET No Upsets: >100 MEV-cm
2
/mg
Single Event Upset (SEU) Immunity < 2 x 10
-9
Errors/
Bit-Day (Typ)
Dose Rate Survivability: >1 x 10
12
RAD (Si)/s
Dose Rate Upset >10
10
RAD (Si)/s 20ns Pulse
Latch-Up Free Under Any Conditions
Fanout (Over Temperature Range)
- Bus Driver Outputs: 15 LSTTL Loads
Military Temperature Range: -55
o
C to +125
o
C
Significant Power Reduction Compared to LSTTL ICs
DC Operating Voltage Range: 4.5V to 5.5V
LSTTL Input Compatibility
- VIL = 0.8V Max
- VIH = VCC/2 Min
Input Current Levels Ii
≤
5
μ
A @ VOL, VOH
Description
The Intersil HCTS365MS is a Radiation Hardened non-
inverting hex buffer and line driver with Tri-state outputs. The
output enables (OE1 and OE2) control the three-state out-
puts. If either OE1 or OE2 is high the outputs will be in a
High impedance state. For Data, OE1 and OE2 must be
Low.
The HCTS365MS utilizes advanced CMOS/SOS technology
to achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family
September 1995
Spec Number
518637
File Number
3070.1
相關PDF資料 |
PDF描述 |
|---|---|
| HCTS365HMSR | Radiation Hardened Hex Buffer/Line Driver Non-Inverting |
| HCTS541D | Quadruple 2-Input Positive-NOR Gates 14-CDIP -55 to 125 |
| HCTS541MS | Radiation Hardened Non-Inverting Octal Buffer/Line Driver, Three-State |
| HCTS541DMSR | Quadruple 2-Input Positive-NOR Gates 14-CFP -55 to 125 |
| HCTS541K | Hex Inverters 20-LCCC -55 to 125 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| HCTS373D | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Octal Transparent Latch, Three-State |
| HCTS373DMSR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Octal Transparent Latch, Three-State |
| HCTS373DTR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Octal Transparent Latch, Three-State |
| HCTS373HMSR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Octal Transparent Latch, Three-State |
| HCTS373K | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Octal Transparent Latch, Three-State |
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