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參數資料
| 型號： | HCTS393K |
| 廠商： | Intersil Corporation |
| 英文描述： | Test Bus Controllers 68-CPGA -55 to 125 |
| 中文描述： | 輻射加固雙4位的二進制計數器 |
| 文件頁數： | 1/9頁 |
| 文件大小： | 145K |
| 代理商： | HCTS393K |
672
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
Ordering Information
PART NUMBER
TEMPERATURE RANGE
SCREENING LEVEL
PACKAGE
HCTS393DMSR
-55
o
C to +125
o
C
Intersil Class S Equivalent
14 Lead SBDIP
HCTS393KMSR
-55
o
C to +125
o
C
Intersil Class S Equivalent
14 Lead Ceramic Flatpack
HCTS393D/Sample
+25
o
C
Sample
14 Lead SBDIP
HCTS393K/Sample
+25
o
C
Sample
14 Lead Ceramic Flatpack
HCTS393HMSR
+25
o
C
Die
Die
HCTS393MS
Radiation Hardened
Dual 4-Stage Binary Counter
Pinouts
14 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T14
TOP VIEW
14 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP3-F14
TOP VIEW
CP 1
MR 1
Q0 1
Q1 1
Q2 1
Q3 1
GND
VCC
2 CP
2 MR
2 Q0
2 Q1
2 Q2
2 Q3
1
2
3
4
5
6
7
14
13
12
11
10
9
8
14
13
12
11
10
9
8
2
3
4
5
6
7
1
CP 1
MR 1
Q0 1
Q1 1
Q2 1
Q3 1
GND
VCC
2 CP
2 MR
2 Q0
2 Q1
2 Q2
2 Q3
Features
3 Micron Radiation Hardened CMOS SOS
Total Dose 200K RAD (Si)
SEP Effective LET No Upsets: >100 MEV-cm
2
/mg
Single Event Upset (SEU) Immunity < 2 x 10
-9
Errors/
Bit-Day (Typ)
Dose Rate Survivability: >1 x 10
12
RAD (Si)/s
Dose Rate Upset >10
10
RAD (Si)/s 20ns Pulse
Latch-Up Free Under Any Conditions
Fanout (Over Temperature Range)
- Standard Outputs: 10 LSTTL Loads
Military Temperature Range: -55
o
C to +125
o
C
Significant Power Reduction Compared to LSTTL ICs
DC Operating Voltage Range: 4.5V to 5.5V
LSTTL Input Compatibility
- VIL = 0.8V Max
- VIH = VCC/2 Min
Input Current Levels Ii
≤
5
μ
A at VOL, VOH
Description
The Intersil HCTS393MS is a Radiation Hardened 4-stage
riple-carry binary counter. All counter stages are master-
slave flip-flop. The state of the stage advances one count on
the negative transition of each clock pulse. A high voltage
level on the MR line resets all counters to their zero state. All
inputs and outputs are buffered.
The HCTS393MS utilizes advanced CMOS/SOS technology
to achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCTS393MS is supplied in a 14 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
August 1995
Spec Number
518633
File Number
3071.1
D
相關PDF資料 |
PDF描述 |
|---|---|
| HCTS393MS | Test Bus Controllers 68-CPGA -55 to 125 |
| HCTS393HMSR | Radiation Hardened Dual 4-Stage Binary Counter |
| HCTS4002HMSR | Radiation Hardened Dual 4-Input NOR Gate |
| HCTS4002D | Radiation Hardened Dual 4-Input NOR Gate |
| HCTS4002DMSR | Radiation Hardened Dual 4-Input NOR Gate |
相關代理商/技術參數 |
參數描述 |
|---|---|
| HCTS393KMSR | 制造商:Intersil Corporation 功能描述:COUNTER DUAL 4BIT BINARY UP 14PIN CFLATPACK - Bulk |
| HCTS393MS | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Dual 4-Stage Binary Counter |
| HCTS4002D | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Dual 4-Input NOR Gate |
| HCTS4002DMSR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Dual 4-Input NOR Gate |
| HCTS4002HMSR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Dual 4-Input NOR Gate |
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