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參數資料
| 型號： | HCTS646MS |
| 廠商： | Intersil Corporation |
| 英文描述： | Radiation Hardened Octal Bus Transceiver/Register, Three-State |
| 中文描述： | 輻射加固八路總線收發器/注冊，三態 |
| 文件頁數： | 1/11頁 |
| 文件大小： | 147K |
| 代理商： | HCTS646MS |
706
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
Ordering Information
PART NUMBER
TEMPERATURE RANGE
-55
o
C to +125
o
C
-55
o
C to +125
o
C
+25
o
C
+25
o
C
+25
o
C
SCREENING LEVEL
PACKAGE
HCTS646DMSR
Intersil Class S Equivalent
24 Lead SBDIP
HCTS646KMSR
Intersil Class S Equivalent
24 Lead Ceramic Flatpack
HCTS646D/Sample
Sample
24 Lead SBDIP
HCTS646K/Sample
Sample
24 Lead Ceramic Flatpack
HCTS646HMSR
Die
Die
HCTS646MS
Radiation Hardened
Octal Bus Transceiver/Register, Three-State
Pinouts
24 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T24
TOP VIEW
24 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP4-F24
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
CAB
SAB
DIR
A0
A1
A2
A3
A4
A5
A6
A7
GND
16
17
18
19
20
21
22
23
24
15
14
13
VCC
SBA
OE
B0
B1
B3
B5
B6
B7
CBA
B2
B4
24
23
22
21
20
19
18
17
16
15
14
13
2
3
4
5
6
7
8
9
10
11
12
1
CAB
SAB
DIR
A0
A1
A2
A3
A4
A5
A6
A7
GND
VCC
CBA
SBA
OE
B0
B1
B2
B3
B4
B5
B6
B7
Features
3 Micron Radiation Hardened CMOS SOS
Total Dose 200K RAD (Si)
SEP Effective LET No Upsets: >100 MEV-cm
2
/mg
Single Event Upset (SEU) Immunity < 2 x 10
-9
Errors/
Bit-Day (Typ)
Dose Rate Survivability: >1 x 10
12
RAD (Si)/s
Dose Rate Upset >10
10
RAD (Si)/s 20ns Pulse
Cosmic Ray Upset Rate 2 x 10
-9
Errors/Bit Day
Latch-Up Free Under Any Conditions
Fanout (Over Temperature Range)
- Bus Driver Outputs - 15 LSTTL Loads
Military Temperature Range: -55
o
C to +125
o
C
Significant Power Reduction Compared to LSTTL ICs
DC Operating Voltage Range: 4.5V to 5.5V
LSTTL Input Compatibility
- VIL = 0.8V Max
- VIH = VCC/2
Input Current Levels Ii
≤
5
μ
A at VOL, VOH
Description
The Intersil HCTS646MS is a Radiation Hardened Three-
State Octal Bus Tranceiver/Register with Non-Inverting
outputs. This device is a bus transceiver with D-type flip-flops
which act as internal storage registers. Data on the A bus or
the B bus can be clocked into the registers on a High-to-Low
transition of either CAB ro CBA clock inputs. Output enable
(OE) and Direction (DIR) inputs control the transceiver func-
tions. Data present at the high impedance output can be
stored in either register or both but only one of the two buses
can be enabled as outputs at any one time. The select con-
trols (SAB and SBA) can multiplex stored and transparent
(real time) data. The direction control determines which data
bus will receive data when the OE pin is LOW. In the high
impedance mode (OE high), A data can be stored in one reg-
ister and B data in the other register. Data at the A or B termi-
nals can be clocked into the storage flip-flops at any time.
The HCTS646MS utilizes advanced CMOS/SOS technology
to achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCTS646MS is supplied in a 24 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
August 1995
Spec Number
518628
File Number
3074.1
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