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參數(shù)資料
| 型號： | HCTS74KMSR |
| 廠商： | INTERSIL CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATORS 16-CFP -55 to 125 |
| 中文描述： | HCT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP14 |
| 封裝： | CERAMIC, DFP-14 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大小： | 176K |
| 代理商： | HCTS74KMSR |
460
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
Ordering Information
PART NUMBER
TEMPERATURE RANGE
SCREENING LEVEL
PACKAGE
HCTS74DMSR
-55
o
C to +125
o
C
Intersil Class S Equivalent
14 Lead SBDIP
HCTS74KMSR
-55
o
C to +125
o
C
Intersil Class S Equivalent
14 Lead Ceramic Flatpack
HCTS74D/Sample
+25
o
C
Sample
14 Lead SBDIP
HCTS74K/Sample
+25
o
C
Sample
14 Lead Ceramic Flatpack
HCTS74HMSR
+25
o
C
Die
Die
HCTS74MS
Radiation Hardened Dual-D
Flip-Flop with Set and Reset
Pinouts
14 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-183S CDIP2-T14, LEAD FINISH C
TOP VIEW
14 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-183S CDFP3-F14, LEAD FINISH C
TOP VIEW
R1
D1
CP1
S1
Q1
Q1
GND
VCC
R2
D2
CP2
S2
Q2
Q2
1
2
3
4
5
6
7
14
13
12
11
10
9
8
14
13
12
11
10
9
8
2
3
4
5
6
7
1
R1
D1
CP1
S1
Q1
Q1
GND
VCC
R2
D2
CP2
S2
Q2
Q2
Features
3 Micron Radiation Hardened SOS CMOS
Total Dose 200K RAD (Si)
SEP Effective LET No Upsets: >100 MEV-cm
2
/mg
Single Event Upset (SEU) Immunity < 2 x 10
-9
Errors/
Bit-Day (Typ)
Dose Rate Survivability: >1 x 10
12
RAD (Si)/s
Dose Rate Upset >10
10
RAD (Si)/s 20ns Pulse
Latch-Up Free Under Any Conditions
Military Temperature Range: -55
o
C to +125
o
C
Significant Power Reduction Compared to LSTTL ICs
DC Operating Voltage Range: 4.5V to 5.5V
LSTTL Input Compatibility
- VIL = 0.8V Max
- VIH = VCC/2 Min
Input Current Levels Ii
≤
5
μ
A at VOL, VOH
Description
The Intersil HCTS74MS is a Radiation Hardened positive
edge triggered flip-flop with set and reset.
The HCTS74MS utilizes advanced CMOS/SOS technology
to achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCTS74MS is supplied in a 14 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
September 1995
Spec Number
518626
File Number
2143.2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HCTS86HMSR | Radiation Hardened Quad 2-Input Exclusive OR Gate |
| HCTS86D | Quadruple Bus Buffer Gates With 3-State Outputs 14-CDIP -55 to 125 |
| HCTS86DMSR | Quadruple Bus Buffer Gates With 3-State Outputs 14-CFP -55 to 125 |
| HCTS86K | Quadruple Bus Buffer Gates With 3-State Outputs 20-LCCC -55 to 125 |
| HCTS86KMSR | Quadruple Bus Buffer Gates With 3-State Outputs 14-CDIP -55 to 125 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HCTS74KTR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Dual-D Flip-Flop with Set and Reset |
| HCTS74MS | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Dual-D Flip-Flop with Set and Reset |
| HCTS74T | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Dual-D Flip-Flop with Set and Reset |
| HCTS75D | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Dual 2-Bit Bistable Transparent Latch |
| HCTS75DMSR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Dual 2-Bit Bistable Transparent Latch |
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