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參數(shù)資料
| 型號： | HCTS75K |
| 廠商： | Intersil Corporation |
| 英文描述： | Quadruple Bus Buffer Gates With 3- State Outputs 14-CDIP -55 to 125 |
| 中文描述： | 輻射加固雙2位雙穩(wěn)態(tài)透明鎖存器 |
| 文件頁數(shù)： | 7/9頁 |
| 文件大小： | 136K |
| 代理商： | HCTS75K |
476
HCTS75MS
Propagation Delay Timing Diagram and Load Circuit
Transition Timing Diagram
Pulse Width, Setup, Hold Timing Diagram and Load Circuit
Pulse Width, Setup, Hold Timing Diagram Negative Edge Trigger and Load Circuit
VS
INPUT
OUTPUT
VIH
VSS
VOH
VOL
TPLH
TPHL
VS
DUT
TEST
50pF
500
OUTPUT
TTHL
80%
20%
80%
20%
VOH
VOL
TTLH
VOLTAGE LEVELS
PARAMETER
VCC
VIH
VS
VIL
GND
HCTS
4.50
3.00
1.30
0
0
UNITS
V
V
V
V
V
TH
D INPUT
VIH
VIL
VS
VS
TSU
TW
E INPUT
VIH
TH = Hold Time
TSU = Setup Time
TW = Pulse Width
VIL
VOLTAGE LEVELS
PARAMETER
VCC
VIH
VS
VIL
GND
HCTS
4.50
4.50
2.25
0
0
UNITS
V
V
V
V
V
DUT
TEST
50pF
500
TH
INPUT
VIH
VIL
VS
VS
TSU
TW
INPUT CP
VIH
TH = Hold Time
TSU = Setup Time
TW = Pulse Width
VIL
TW
VOLTAGE LEVELS
PARAMETER
VCC
VIH
VS
VIL
GND
HCTS
4.50
4.50
2.25
0
0
UNITS
V
V
V
V
V
DUT
TEST
50pF
500
Spec Number
518625
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HCTS75KMSR | Quadruple Bus Buffer Gates With 3- State Outputs 14-CFP -55 to 125 |
| HCTS75MS | Quadruple Bus Buffer Gates With 3-State Outputs 20-LCCC -55 to 125 |
| HCTS75HMSR | Radiation Hardened Dual 2-Bit Bistable Transparent Latch |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HCTS75KMSR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Dual 2-Bit Bistable Transparent Latch |
| HCTS75MS | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Dual 2-Bit Bistable Transparent Latch |
| HCTS85D | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened 4-Bit Magnitude Comparator |
| HCTS85DMSR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened 4-Bit Magnitude Comparator |
| HCTS85HMSR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened 4-Bit Magnitude Comparator |
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