參數資料
| 型號： | HD3-4702-9Z |
| 廠商： | Intersil |
| 文件頁數： | 1/8頁 |
| 文件大小： | 0K |
| 描述： | IC BIT RATE GEN CMOS 16-PDIP |
| 標準包裝： | 250 |
| 類型： | 比特率發生器 |
| PLL： | 無 |
| 輸入： | 時鐘，晶體 |
| 輸出： | 時鐘 |
| 電路數： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 1MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 16-DIP（0.300"，7.62mm） |
| 供應商設備封裝： | 16-PDIP |
| 包裝： | 管件 |
1
FN2954.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HD-4702
CMOS Programmable Bit Rate Generator
The HD-4702 Bit Rate Generator provides the necessary
clock signals for digital data transmission systems, such as a
UART. It generates 13 commonly used bit rates using an on-
chip crystal oscillator or an external input. For conventional
operation generating 16 output clock pulses per bit period,
the input clock frequency must be 2.4576MHz (i.e. 9600
Baud x 16 x 16, since there is an internal 16 prescaler). A
lower input frequency will result in a proportionally lower
output frequency.
The HD-4702 can provide multi-channel operation with a
minimum of external logic by having the clock frequency CO
and the 8 prescaler outputs Q0, Q1, Q2 available externally.
All signals have a 50% duty cycle except 1800 Baud, which
has less than 0.39% distortion.
The four rate select inputs (S0-S3) select which bit rate is at
the output (Z). See Truth Table for Rate Select Inputs for
select code and output bit rate. Two of the 16 select codes for
the HD-4702 do not select an internally generated frequency,
but select an input into which the user can feed either a
different frequency, or a static level (High or Low) to generate
“ZERO BAUD”.
The bit rates most commonly used in modern data terminals
(110, 150, 300, 1200, 2400 Baud) require that no more than
one input be grounded for the HD-4702, which is easily
achieved with a single 5-position switch.
The HD-4702 has an initialization circuit which generates a
master reset for the scan counter. This signal is derived from
a digital differentiator that senses the first high level on the
CP input after the ECP input goes low. When ECP is high,
selecting the crystal input, CP must be low. A high level on
CP would apply a continuous reset. See Clock Modes and
Initialization below.
Features
HD-4702 Provides 13 Commonly Used Bit Rates
Uses a 2.4576MHz Crystal/Input for Standard Frequency
Output (16 Times Bit Rate)
Low Power Dissipation
Conforms to EIA RS-404
One HD-4702 Controls up to Eight Transmission
Channels
Initialization Circuit Facilitates Diagnostic Fault Isolation
On-Chip Input Pull-Up Circuit
Truth Table
Pinout
HD-4702 (16 Ld PDIP)
TOP VIEW
Ordering Information
PACKAGE
TEMP.
RANGE
(oC)
PART
NUMBER
PART
MARKING
PKG.
NO.
PDIP
-40 to +85
HD3-4702-9
E16.3
PDIP
(Pb-free)
-40 to +85
HD3-4702-9Z*
HD3-4702-9Z
E16.3
CerDIP
SMD#
-55 to +125 5962-9051801MEA
F16.3
*Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
TRUTH TABLE FOR RATE SELECT INPUTS
(Using 2.4576MHz Crystal)
S3
S2
S1
S0
OUTPUT RATE (Z)
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
MUX Input (IM)
50 Baud
75 Baud
134.5 Baud
200 Baud
600 Baud
2400 Baud
9600 Baud
4800 Baud
1800 Baud
1200 Baud
2400 Baud
300 Baud
150 Baud
110 Baud
NOTE: 19200 Baud by connecting Q2 to IM.
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
Q0
Q1
Q2
ECP
CP
OX
GND
IX
VCC
S0
S1
S2
S3
Z
CO
IM
Data Sheet
August 24, 2006
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