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參數資料
| 型號： | HD4702 |
| 廠商： | Intersil Corporation |
| 英文描述： | CMOS Programmable Bit Rate Generator |
| 中文描述： | CMOS可編程比特率發生器 |
| 文件頁數： | 1/8頁 |
| 文件大小： | 80K |
| 代理商： | HD4702 |
1
June 1998
HD-4702/883
CMOS Programmable Bit Rate Generator
Features
This Circuit is Processed in Accordance to MIL-STD-883
and is Fully Conformant Under the Provisions of
Paragraph 1. 2. 1.
HD-4702/883 Provides 13 Commonly Used Bit Rates
Uses a 2.4576MHz Crystal/Input for Standard
Frequency Output (16 Times Bit Rate)
Low Power Dissipation
Conforms to ElA RS-404
One HD-4702/883 Controls up to Eight Transmission
Channels
Initialization Circuit Facilitates Diagnostic Fault
Isolation
On-Chip Input Pull-Up Circuit
Description
The
necessary clock signals for digital data transmission sys-
tems, such as a UART. It generates 13 commonly used bit
rates using an on-chip crystal oscillator or an external input.
For conventional operation generating 16 output clock
pulses per bit period, the input clock frequency must be
2.4576MHz (i.e., 9600 Baud x 16 x 16, since there is an
internal
÷
16 prescaler). A lower input frequency will result in
a proportionally lower output frequency.
HD-4702/883
Bit
Rate
Generator
provides
the
The HD-4702/883 can provide multi-channel operation with
a minimum of external logic by having the clock frequency
C
O
and the
÷
8 prescaler outputs Q
0
, Q
1
, Q
2
available
externally. All signals have a 50% duty cycle except 1800
Baud, which has less than 0.39% distortion.
The four rate select inputs (S
0
-S
3
) select which bit rate is at
the output (Z). See Truth Table for Rate Select Inputs for
select code and output bit rate. Two of the 16 select codes
for the HD-4702/883 do not select an internally generated
frequency, but select an input into which the user can feed
either a different frequency, or a static level (High or Low) to
generate “ZERO BAUD”.
The bit rates most commonly used in modern data terminals
(110,150, 300,1200, 2400 Baud) require that no more than
one input be grounded for the HD-4702/883, which is easily
achieved with a single 5-position switch.
The
generates a master reset for the scan counter. This signal is
derived from a digital differentiator that senses the first high
level on the C
P
input after the E
CP
input goes low. When
E
CP
is high, selecting the crystal input, C
P
must be low. A
high level on C
P
would apply a continuous reset. See Clock
Modes and Initialization below.
HD-4702/883
has
an
initialization
circuit
which
Pinout
HD-4702/883 (CERDIP)
TOP VIEW
Ordering Information
PART
NUMBER
TEMPERATURE
RANGE (
o
C)
PACKAGE
PKG. NO.
HD1-4702/883
-55 to 125
CERDIP
F16.3
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
Q
0
Q
1
Q
2
E
CP
C
P
O
X
GND
I
X
V
CC
I
M
S
0
S
1
S
2
Z
S
3
C
O
File Number
2955.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
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相關代理商/技術參數 |
參數描述 |
|---|---|
| HD-4702 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Programmable Bit Rate Generator |
| HD-4702/883 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Programmable Bit Rate Generator |
| HD-4702_06 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Programmable Bit Rate Generator |
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