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參數(shù)資料
| 型號(hào)： | HD74ACT112 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | Dual JK Negative Edge-Triggered Flip-Flop |
| 中文描述： | 雙JK負(fù)邊沿觸發(fā)器 |
| 文件頁(yè)數(shù)： | 1/10頁(yè) |
| 文件大小： | 59K |
| 代理商： | HD74ACT112 |
HD74AC112/HD74ACT112
Dual JK Negative Edge-Triggered Flip-Flop
Description
The HD74AC112/HD74ACT112 features individual J, K, Clock and asynchronous Set and Clear inputs to
each flip-flop. When the clock goes High, the inputs are enabled and data will be accepted. The logic level
of the J and K inputs may change when the clock is High and the bistable will perform according to the
Truth Table as long as minimum setup and hold times are observed. Input data is transferred to the outputs
on the falling edge of the clock pulse.
Features
Outputs Source/Sink 24 mA
HD74ACT112 has TTL-Compatible Inputs
Pin Arrangement
1
2
3
4
5
6
7
8
CP
1
K
1
J
1
S
D1
Q
1
Q
1
Q
2
GND
V
CC
C
D1
C
D2
CP
2
K
2
J
2
S
D2
Q
2
16
15
14
13
12
11
10
9
(Top view)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HD74AC112 | Dual JK Negative Edge-Triggered Flip-Flop(下降沿觸發(fā)雙JK觸發(fā)器) |
| HD74ACT161 | Synchronous Presettable Binary Counter(同步預(yù)置二進(jìn)制計(jì)數(shù)器) |
| HD74ACT163 | Synchronous Presettable Binary Counter(同步預(yù)置二進(jìn)制計(jì)數(shù)器) |
| HD74ACT280 | 9-bit Parity Generator/Checker |
| HD74AC280 | Octal Buffers And Drivers With 3-State Outputs 20-LCCC -55 to 125 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HD74ACT112FP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:J-K-Type Flip-Flop |
| HD74ACT112P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:J-K-Type Flip-Flop |
| HD74ACT112RP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FLIP-FLOP|DUAL|J/K TYPE|ACT-CMOS|SOP|16PIN|PLASTIC |
| HD74ACT112T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FLIP-FLOP|DUAL|J/K TYPE|ACT-CMOS|TSSOP|16PIN|PLASTIC |
| HD74ACT125 | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:Quad Buffer/Line Driver with 3-State Output |
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