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參數資料
| 型號： | HD74HC195 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 4-bit Parallel-Access Shift Register |
| 中文描述： | 4位并行存取移位寄存器 |
| 文件頁數： | 1/9頁 |
| 文件大小： | 50K |
| 代理商： | HD74HC195 |
HD74HC195
4-bit Parallel-Access Shift Register
Description
This shift register features parallel inputs, parallel outputs, J-
K
serial inputs, Shift/Load control input, and a
direct overriding clear. This shift register can operate in two modes: Parallel load; shift from Q
A
towards
Q
D
.
Paralle loading is accomplished by applying the four bits of data, and taking the Shift/Load control Input
low. The data is loaded into the associated flip-flops and appears at the outputs after the positive transition
of the clock input. During parallel loading, serial data flow is inhibited. Serial shifting occurs
synchronously when the Shift/Load control input is high. Serial data for this mode is entered at the J-
K
inputs. These inputs allow the first stage to perform as a J-
K
or toggle flip-flop as shown in the function
table.
Features
High Speed Operation: t
pd
(Clock to Q) = 13 ns typ (C
L
= 50 pF)
High Output Current: Fanout of 10 LSTTL Loads
Wide Operating Voltage: V
CC
= 2 to 6 V
Low Input Current: 1 μA max
Low Quiescent Supply Current: I
CC
(static) = 4 μA max (Ta = 25°C)
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