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參數(shù)資料
| 型號(hào)： | HD74SSTV16857 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 1:1 14-bit SSTL_2 Registered Buffer(1:1 14-位 SSTL_2 寄存緩沖器) |
| 中文描述： | 1:1 14位SSTL_2注冊(cè)緩沖區(qū)（1:1 14 -位SSTL_2寄存緩沖器） |
| 文件頁(yè)數(shù)： | 1/15頁(yè) |
| 文件大小： | 64K |
| 代理商： | HD74SSTV16857 |
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HD74SSTV16857
1:1 14-bit SSTL_2 Registered Buffer
ADE-205-336E (Z)
6th. Edition
May 2000
Description
The HD74SSTV16857 is a 14-bit registered buffer designed for 2.3 V to 2.7 V Vcc operation and
LVCMOS reset (
RESET
) input / SSTL_2 data (D) inputs and CLK input.
Data flow from D to Q is controlled by differential clock pins (CLK,
CLK
) and the
RESET
. Data is
triggered on the positive edge of the positive clock (CLK), and the negative clock (
CLK
) must be used to
maintain noise margins. When
RESET
is low, all registers are reset and all outputs are low.
To ensure defined outputs from the register before a stable clock has been supplied,
RESET
must be held in
the low state during power up.
Features
Supports LVCMOS reset (
RESET
) input / SSTL_2 data (D) inputs and CLK input
Differential SSTL_2 (Stub series terminated logic) CLK signal
Flow through architecture optimizes PCB layout
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| HD74SSTV16859 | 1:2 13-bit SSTL_2 Registered Buffer(1:2 13-位 SSTL_2 寄存緩沖器) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HD74SSTV16857TE | 功能描述:IC REG BUFFER 14-BIT 48TSSOP RoHS:否 類別:集成電路 (IC) >> 邏輯 - 專用邏輯 系列:74SSTV 產(chǎn)品變化通告:Product Discontinuation 25/Apr/2012 標(biāo)準(zhǔn)包裝:1,500 系列:74SSTV 邏輯類型:DDR 的寄存緩沖器 電源電壓:2.3 V ~ 2.7 V 位數(shù):14 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:48-TFSOP（0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:48-TSSOP 包裝:帶卷 (TR) |
| HD74SSTV16859TE | 制造商:Renesas Electronics Corporation 功能描述:REGISTERED BFFR SGL 13-CH CMOS 64TSSOP - Tape and Reel |
| HD74UH08EL | 制造商:Renesas Electronics Corporation 功能描述:UNI LOGIC SERIES 2 INPUT |
| HD74UH4066(EL-E) | 制造商:Renesas Electronics Corporation 功能描述: |
| HD750 | 制造商:EXTECH-FLIR COMMERCIAL SYSTEMS 功能描述:MANOMETER WITH SOFTWARE, 5PSI 制造商:Extech 功能描述:Differential Pressure Manometer,Large LCD Display With Backlighting |
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