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參數資料
| 型號： | HDD32M72B9 |
| 廠商： | Hanbit Electronics Co.,Ltd. |
| 英文描述： | DDR SDRAM Module 256Mbyte (32Mx72bit), based on32Mx8,4Banks, 8K Ref., ECC Unbuffered SO-DIMM |
| 中文描述： | 256MB的DDR SDRAM內存模塊（32Mx72bit）根據on32Mx8，4Banks，8K的參考。，ECC無緩沖的SO - DIMM |
| 文件頁數： | 1/12頁 |
| 文件大小： | 210K |
| 代理商： | HDD32M72B9 |
HANBit
HDD32M72B9
URL : www.hbe.co.kr 1 HANBit Electronics Co.,Ltd.
REV 1.0 (July. 2003)
GENERAL DESCRIPTION
The HDD32M72B9 is a 32M x 72 bit Double Data Rate(DDR) Synchronous Dynamic RAM high-density memory module.
The module consists of nine CMOS 32M x 8 bit with 4banks DDR SDRAMs in 66pin TSOP-II 400mil packages and 2K
EEPROM in 8-pin TSSOP package on a 200-pin glass-epoxy. Four 0.1uF decoupling capacitors are mounted on the printed
circuit board in parallel for each DDR SDRAM. The HDD32M72B9 is a SO-DIMM(Small Outline Dual in line Memory
Module) .Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible
on both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allows the same device
to be useful for a variety of high bandwidth, high performance memory system applications. All module components may be
powered from a single 2.5V DC power supply and all inputs and outputs are SSTL_2 compatible.
FEATURES
Part Identification
HDD32M72B9
–
16B : 166MHz (CL=2.5)
HDD32M72B9
–
13A : 133MHz (CL=2)
HDD32M72B9
–
13B : 133MHz (CL=2.5)
256MB(32Mx64) Unbuffered DDR SO-DIMM based on 32Mx8 DDR SDRSM with ECC
2.5V
±
0.2V VDD and VDDQ power supply
Auto & self refresh capability (8192 Cycles/64ms)
All input and output are compatible with SSTL_2 interface
Data(DQ), Data strobes and write masks latched on the rising and falling edges of the clock
All Addresses and control inputs except Data(DQ), Data strobes and Data masks latched on the rising edges of the clock
MRS cycle with address key programs
- Latency (Access from column address) : 2, 2.5
- Burst length : 2, 4, 8
- Burst type : Sequential & Interleave
Data(DQ), Data strobes and write masks latched on the rising and falling edges of the clock
All Addresses and control inputs except Data(DQ), Data strobes and Data masks latched on the rising edges of the clock
The used device is 8M x 8bit x 4Banks DDR SDRAM
Auto & Self refresh, 7.8us refresh interval (8K/64ms refresh)
Serial Presence detect with EEPROM
DDR SDRAM Module 256Mbyte (32Mx72bit), based on32Mx8,4Banks,
8K Ref., ECC Unbuffered SO-DIMM Part No. HDD32M72B9
相關PDF資料 |
PDF描述 |
|---|---|
| HDD32M72B9-13A | DDR SDRAM Module 256Mbyte (32Mx72bit), based on32Mx8,4Banks, 8K Ref., ECC Unbuffered SO-DIMM |
| HDD32M72B9-13B | DDR SDRAM Module 256Mbyte (32Mx72bit), based on32Mx8,4Banks, 8K Ref., ECC Unbuffered SO-DIMM |
| HDD32M72B9-16B | DDR SDRAM Module 256Mbyte (32Mx72bit), based on32Mx8,4Banks, 8K Ref., ECC Unbuffered SO-DIMM |
| HDD32M72D9RPW | DDR SDRAM Module 256Mbyte (32Mx72bit), based on 32Mx8, 4Banks 8K Ref., 184Pin-DIMM with PLL & Register |
| HDD32M72D9RPW-10A | DDR SDRAM Module 256Mbyte (32Mx72bit), based on 32Mx8, 4Banks 8K Ref., 184Pin-DIMM with PLL & Register |
相關代理商/技術參數 |
參數描述 |
|---|---|
| HDD32M72B9-13A | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 256Mbyte (32Mx72bit), based on32Mx8,4Banks, 8K Ref., ECC Unbuffered SO-DIMM |
| HDD32M72B9-13B | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 256Mbyte (32Mx72bit), based on32Mx8,4Banks, 8K Ref., ECC Unbuffered SO-DIMM |
| HDD32M72B9-16B | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 256Mbyte (32Mx72bit), based on32Mx8,4Banks, 8K Ref., ECC Unbuffered SO-DIMM |
| HDD32M72D18RPW | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 256Mbyte (32Mx72bit), based on 16Mx8, 4Banks, 4K Ref., 184Pin-DIMM with PLL & Register |
| HDD32M72D9RPW | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 256Mbyte (32Mx72bit), based on 32Mx8, 4Banks 8K Ref., 184Pin-DIMM with PLL & Register |
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