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參數資料
| 型號： | HEC4040BT,112 |
| 廠商： | NXP Semiconductors |
| 文件頁數： | 1/14頁 |
| 文件大小： | 0K |
| 描述： | IC 12STAGE BINARY COUNTER 16SOIC |
| 產品培訓模塊： | Logic Packages |
| 標準包裝： | 50 |
| 系列： | 4000B |
| 邏輯類型： | 二進制計數器 |
| 方向： | 上 |
| 元件數： | 1 |
| 每個元件的位元數： | 12 |
| 復位： | 異步 |
| 觸發器類型： | 負邊沿 |
| 電源電壓： | 4.5 V ~ 15.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 16-SO |
| 包裝： | 管件 |
| 其它名稱： | 935249730112 HEC4040BT HEC4040BT-ND |
1.
General description
The HEF4040B is a 12-stage binary ripple counter with a clock input (CP), an overriding
asynchronous master reset input (MR) and twelve fully buffered outputs (Q0 to Q11). The
counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter
stages and forces all outputs LOW, independent of CP. Each counter stage is a static
toggle flip-flop. The clock input is highly tolerant of slow rise and fall times due to its
Schmitt trigger action.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
2.
Features and benefits
Tolerant of slow clock rise and fall time
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from
40 C to +85 C
Complies with JEDEC standard JESD 13-B
3.
Applications
Frequency dividing circuits
Time delay circuits
Control counters
4.
Ordering information
HEF4040B
12-stage binary ripple counter
Rev. 8 — 17 November 2011
Product data sheet
Table 1.
Ordering information
All types operate from
40 C to +85 C.
Type number
Package
Name
Description
Version
HEF4040BP
DIP16
plastic dual in-line package; 16 leads (300 mil)
SOT38-4
HEF4040BT
SO16
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
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