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| 型號： | HFA3824 |
| 廠商： | Intersil Corporation |
| 英文描述： | () |
| 中文描述： | （） |
| 文件頁數(shù)： | 1/2頁 |
| 文件大小： | 21K |
| 代理商： | HFA3824 |
4-253
AN9701.1
CRC-16 Algorithm for Packetized WLAN
Protocols on the HFA3824
Introduction
In packetize RF data transmissions
systems, transmitted messages are
susceptible to various types of bit errors
due to noise, interference, data
collisions, and multipath in a given RF
channel. The main purpose of error detection algorithms is
to enable an RF receiver of a transmitted message to
determine if the message is corrupted. There are various
types of error detection algorithms to chose from. The most
common method for detecting bits errors in messages is
through the use of CRCs (Cyclic Redundancy Codes).
CRCs are very useful in detecting single bit errors, multiple
bit errors, and burst errors in packetized messages. In theory
CRCs could be thought of as simply taking a binary
message and dividing it by a fixed binary number, with the
remainder being the checksum, or more commonly the CRC.
The fixed binary number is the divisor commonly called the
polynomial. The CRC-16 algorithm is specified by the
IEEE802.11 for use in the direct sequence physical layer
PLCP (Physical Layer Convergence Protocol). The CCITT
CRC-16 is a standardized algorithm with origins to the
CCITT standards body. The polynomial for the CRC
calculation is a 16-bit function and is given as Gx = X
16
+
X
12
+ X
5
+1. The mathematics performed on in calculating
the CRC is binary modulo 2 arithmetic, and typically
implemented with an XOR function.
CRC16 Algorithm Implementation
The HFA3824 implements the specified IEEE802.11 CRC
function. The CRC can be programmed to protect the PLCP
header fields. Any error detected by the CRC on the header
will flag the MAC and the package will be dropped. The
HFA3824 can be programmed to process the packet
independent of the CRC indication. This mode may be
applicable for non - IEEE802.11 Applications.
In this mode the HFA3824 can is configured to pass the data
to the MAC even when a CRC error has occurred. In this case
the MAC can decide on how the packet data can be used.
There are various ways to implement a CRC algorithm in
software and hardware. Processing the IEEE802.11 PLCP
DS-PHY header is a time critical function, which favors a
hardware approach. A typical implementation is illustrated in
Figure 1. The CRC calculator illustrated uses a 16-bit D-
Flipflop Shift Register an three XOR gates to perform the
modulo 2 arithmetic. Only the coefficient taps in the
polynomial are used with the XOR gates for modulo 2
arithmetic. The message is shifted in serially MSB first. The
resultant 16-bit parallel output is the remainder, inverted and
appended as the checksum of the message. The CRC
checker at the receive end needs to be initialized with an all
“1's” value. The CRC check engine will calculate the proper
sum assuming that an all 1's value has been used as the
initialization seed. The CRC generator will lock if it is initially
seeded with a value of all zeros. This initial condition needs
to be avoided.
CRC16 Protected Fields in the PLCP Header
The CCITT CRC-16 is calculated bit serially in the HFA3824
protecting the Signal, Service and Length fields of the PLCP
header. Figure 2 illustrates the Preamble and PLCP header
used for IEEE802.11 data transmission. This feature is
enabled in the HFA3824 by asserting bits 3 and 4 of Control
Register CR# 0 to a logic “1”. Before the PLCP header is
transmitted a CRC-16 checksum calculated and appended
to the length field. The Signal, Service and Length fields of
the PLCP header are clocked bit serially (MSB) first through
a shift register, and multiplied by tapped branches
corresponding to the polynomial Gx = X
16
+ X
12
+ X
5
+1.
Typically CRC algorithms initialize their shift registers to
some known value. For the IEEE802.11 algorithm a value of
all ones has been chosen. The initialization value has no
impact on the performance of the CRC calculation.
Initialization only provides a starting point for processing the
checksum. In some cases, it is possible for the data in the
signal and service fields to be zero values.
After the 32 bits of the PLCP header are shifted into the
CRC calculator, the remainder a 16-bit value is configured
into a 16-bit word, logically inverted and appended to the
length field as its own field. At the receiving DS-PHY, the
incoming message, is processed through the same
algorithm after the detection of a valid SFD (start-of-frame
delimiter). The CRC-16 is recalculated on the PLCP header
and compared against the transmitted value for bit error
discrepancies. If the calculated checksum of the received
message differs for the transmitted appended value, then the
message is declared corrupt and discarded.
Application Note
October 1998
Authors: Al Petrick, John Fakatselis
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
PRISM and PRISM logo are trademarks of Intersil Corporation.
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相關(guān)代理商/技術(shù)參數(shù) |
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| HFA3824 WAF | 制造商:Harris Corporation 功能描述: |
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