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參數資料
| 型號： | HFA3861BIN |
| 廠商： | INTERSIL CORP |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | Direct Sequence Spread Spectrum Baseband Processor |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, PLASTIC, MS-026ACD, TQFP-64 |
| 文件頁數： | 27/36頁 |
| 文件大小： | 733K |
| 代理商： | HFA3861BIN |
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27
CONFIGURATION REGISTER 25 ADDRESS (32h) R/W AGC RX_IF AND RF
Bits 7
AGC RX_RF, This input drives the RX-RF control if AGC override Enable is set to 1
When Polarity bit (CR26[6]) is zero:
1 = removes 30dB pad
0 = inserts 30dB pad.
Bits 6:0
AGC RX_IF, This CR is input to RF-IF DAC if AGC override Enable (CR 26[2]) is set to 1.
CONFIGURATION REGISTER 26 ADDRESS (34h) R/W AGC TEST MODES
Bits 7
AGC continuous update
0 = disable
1 = allow updates during freeze AGC and AGC_lock. CR26 bit 3 must be a ‘1’ for this mode to work.
See also CR17[7]
Bit 6
rxRFAGC polarity control.
0 = normal
1 = invert
Bit 5
AGC extra update disable. Allows final update when AGC_lock is declared
0 = enable an extra update
1 = disable extra update
Bit 4
AGC lock verify
0 = enable lock verify
1 = disable lock verify
Bit 3
AGC run on freeze. AGC keeps running after acquisition is complete, only signal is updated, no changes to IF or RF gain occur
0 = normal
1 = enabled
Bit 2
AGC override Enable
0 = normal, disabled
1 = enabled, CR25 controls receiver gain in both RF and IF
Bit 1
AGC random I/Q allows random data on AGC 6-bit I/Q inputs if PN is enabled
0 = normal
1 = enabled
Bit 0
AGC test math- always accumulates in gain adjust, always outputs mean power from log table.
0 = normal
1 = enabled
CONFIGURATION REGISTER ADDRESS 27 (36h) R/W AGC RF THRESHOLD
Bit 7
RXRF AGC disable
0 = normal
1 = disables threshold
Bits 6:0
AGC threshold (0-64 range). The rxRfAgc pad is removed if the AGC voltage falls below this threshold.
CONFIGURATION REGISTER ADDRESS 28 (38h) R/W AGC LOW SAT ATTENUATOR
Bits 7:4
Mid sat attenuation (0-30 range). Note: mid sat attenuation is programmed as value times 2. These attenuator steps will occur
if the number of I and Q saturations are greater than the mid and low saturation counts set by CR16.
Bits 3:0
low sat attenuation (0-15 range)
CONFIGURATION REGISTER ADDRESS 29 (3Ah) R/W AGC LOCK WINDOW NEGATIVE SIDE
Bits 7:5
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bits 4:0
AGC lock window negative side. (0-15 range) (outer lock window) Note: set as a positive number, logic will convert to negative.
CONFIGURATION REGISTER ADDRESS 30 (3Ch) R/W CARRIER SENSE 2 SCALE FACTOR
Bits 7:6
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bit 5:0
Carrier Sense 2 scale factor (0-7.875 range) (000000 - 100000). Used when Dot Product is source of CS2 calculation
HFA3861B
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PDF描述 |
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| HFA3861BIN96 | Direct Sequence Spread Spectrum Baseband Processor |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| HFA3861BIN96 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
| HFA3861IV | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
| HFA3861IV96 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
| HFA3863 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
| HFA3863IN | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
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