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參數(shù)資料
| 型號： | HI-307 |
| 廠商： | Intersil Corporation |
| 英文描述： | 32 MCELL 3 VOLT ZERO POWER ISP CPLD - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | CMOS模擬開關(guān) |
| 文件頁數(shù)： | 1/11頁 |
| 文件大小： | 117K |
| 代理商： | HI-307 |
1
TM
File Number
3125.4
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
Intersil and Design is a trademark of Intersil Corporation.
Copyright
Intersil Corporation 2000
HI-301 thru HI-307
CMOS Analog Switches
The HI-301 thru HI-307 series of switches are monolithic
devices fabricated using CMOS technology and the Intersil
dielectric isolation process. These switches feature break
before-make switching, low and nearly constant ON
resistance over the full analog signal range, and low power
dissipation, (a few mW for the Hl-301 and HI-303, a few
hundred mW for the HI-307).
The HI-301 and HI-303 are TTL compatible and have a logic
“0” condition with an input less than 0.8V and a logic “1”
condition with an input greater than 4V. The HI-307 switches
are CMOS compatible and have a low state with an input
less than 3.5V and a high state with an input greater than
11V. (See pinouts for switch conditions with a logic “1” input.)
Features
Analog Signal Range (
±
15V Supplies) . . . . . . . . . .
±
15V
Low Leakage at 25
o
C . . . . . . . . . . . . . . . . . . . . . . . 40pA
Low Leakage at 125
o
C . . . . . . . . . . . . . . . . . . . . . . . 1nA
Low On Resistance at 25
o
C . . . . . . . . . . . . . . . . . . . 35
Break-Before-Make Delay . . . . . . . . . . . . . . . . . . . . 60ns
Charge Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . 30pC
TTL, CMOS Compatible
Symmetrical Switch Elements
Low Operating Power (Typ for Hl-301 and HI-303) . . 1.0mW
Applications
Sample and Hold (i.e., Low Leakage Switching)
Op Amp Gain Switching (i.e., Low On Resistance)
Portable, Battery Operated Circuits
Low Level Switching Circuits
Dual or Single Supply Systems
Functional Diagram
Pinouts
Switch States Shown For A Logic “1” Input
SPST HI-301
(SOIC)
TOP VIEW
DUAL SPDT HI-303 (CERDIP, SOIC)
HI-307 (CERDIP)
TOP VIEW
Ordering Information
PART
NUMBER
TEMP.
RANGE (
o
C)
PACKAGE
PKG. NO.
HI9P0301-5
0 to 75
14 Ld SOIC
M14.15
HI1-0303-2
-55 to 125
14 Ld CERDIP
F14.3
HI1-0303-5
0 to 75
14 Ld CERDIP
F14.3
HI9P0303-5
0 to 75
14 Ld SOIC
M14.15
HI9P0303-9
-40 to 85
14 Ld SOIC
M14.15
HI1-0307-5
0 to 75
14 Ld CERDIP
F14.3
S
N
IN
P
D
LOGIC
SW1
SW2
0
OFF
ON
1
ON
OFF
NC
D
1
NC
S
1
NC
IN
GND
V+
D
2
NC
S
2
NC
NC
V-
1
2
3
4
5
6
7
14
13
12
11
10
9
8
LOGIC
SW1, SW2
SW3, SW4
0
OFF
ON
1
ON
OFF
1
2
3
4
5
6
7
14
13
12
11
10
9
8
NC
S
3
D
3
D
1
S
1
IN
1
GND
V+
S
4
D
4
D
2
S
2
IN
2
V-
Data Sheet
March 2000
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