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參數資料
| 型號： | HI-8106 |
| 廠商： | Holt Integrated Circuits |
| 英文描述： | 256 MACROCELL 3.3 VOLT ISP CPLD - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | 可編程分頻器與振蕩器或時鐘 |
| 文件頁數： | 1/5頁 |
| 文件大小： | 111K |
| 代理商： | HI-8106 |
HI-8105 & HI-8106
DESCRIPTION
FEATURES
PIN CONFIGURATION
SUPPLY VOLTAGES
FUNCTION TABLE
PIN
1
2
3
4
5
6
7
8
8
SYMBOL
VDD
VSS
OUT
A0
A1
A2
A3
OSC (8105)
CLK (8106)
FUNCTION
SUPPLY
SUPPLY
LOGIC OUTPUT
LOGIC INPUT
LOGIC INPUT
LOGIC INPUT
LOGIC INPUT
INPUT/OUTPUT
LOGIC INPUT
DESCRIPTION
POSITIVE SUPPLY, 1V TO 5V
GROUND
CMOS
CMOS
CMOS
CMOS
CMOS
RC - CONNECT TO VDD
CMOS
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
OUT
DIV by 2
4
8
16
32
64
128
256
512
1024
2048
4096
8192
16384
32768
65536
January 2001
(DS8105 Rev. A)
01/01
A0
A1
A2
A3
OSC on HI-8105
CLK on HI-8106
VSS
VDD
OUT
2
3
4
5
6
7
8
1
VDD
= 1V to 5V
PIN DESCRIPTION TABLE
The HI-8105 & HI-8106 are silicon gate CMOS devices
designed for 'glue' logic applications. They are simple 16
stage dividers with programmable division. The HI-8105
has a one pin oscillator while the HI-8106 receives a clock
input. The one pin oscillator frequency is set by a resistor
toVDDandthecapacitancetoACgroundatthepin.
The wafer processing enables operation to 1 volt guaran-
teed. Thechipisdesignedforlowpowerperformance. As
a result the maximum output frequency is 5 MHz while the
internallogicwillrunconsiderablyhigher.
A companion version, HI-8107, features a crystal oscillator
circuitanda8stageprogrammabledivider.
{
HOLT INTEGRATED CIRCUITS
1
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| HI-8281CJT | 256 MACROCELL 3.3 VOLT ISP CPLD - NOT RECOMMENDED for NEW DESIGN |
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相關代理商/技術參數 |
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